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SI5330A-B00200-GM PDF预览

SI5330A-B00200-GM

更新时间: 2024-11-19 14:44:43
品牌 Logo 应用领域
芯科 - SILICON 驱动逻辑集成电路
页数 文件大小 规格书
20页 536K
描述
Low Skew Clock Driver, 5330 Series, 4 True Output(s), 0 Inverted Output(s), 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24

SI5330A-B00200-GM 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:QFN包装说明:4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2.1
Is Samacsys:N系列:5330
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N24
长度:4 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:24实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):4 ns
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:0.9 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
最小 fmax:710 MHzBase Number Matches:1

SI5330A-B00200-GM 数据手册

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Si5330  
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW  
CLOCK BUFFER/LEVEL TRANSLATOR  
Features  
Supports single-ended or  
Output-output skew: 100 ps  
Propagation delay: 2.5 ns typ  
differential input clock signals  
Generates four differential  
(LVPECL, LVDS, HCSL) or eight  
single-ended (CMOS, SSTL,  
HSTL) outputs  
Single core supply with excellent  
PSRR: 1.8, 2.5, or 3.3 V  
Output driver supply voltage  
independent of core supply: 1.5,  
1.8, 2.5, or 3.3 V  
Provides signal level translation  
Differential to single-ended  
Single-ended to differential  
Differential to differential  
Single-ended to single-ended  
Wide frequency range  
Loss of Signal (LOS) indicator  
Ordering Information:  
allows system clock monitoring  
See page 14.  
Output Enable (OEB) pin allows  
glitchless control of output clocks  
Low power: 10 mA typical core  
Pin Assignments  
LVPECL, LVDS: 5 to 710 MHz  
HCSL: 5 to 250 MHz  
SSTL, HSTL: 5 to 350 MHz  
CMOS: 5 to 200 MHz  
current  
Industrial temperature range:  
°
–40 to +85 C  
Small size: 24-lead, 4 x 4 mm  
Additive jitter: 150 fs RMS typ  
QFN  
Applications  
High Speed Clock Distribution  
Ethernet Switch/Router  
SONET / SDH  
PCI Express 2.0/3.0  
Fibre Channel  
MSAN/DSLAM/PON  
Telecom Line Cards  
Functional Block Diagram  
Rev. 1.2 4/17  
Copyright © 2017 by Silicon Laboratories  
Si5330  

SI5330A-B00200-GM 替代型号

型号 品牌 替代类型 描述 数据表
SI5330A-A00200-GM SILICON

完全替代

Supports single-ended or differential input clock singnals Generates four differential (LV

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