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SI5326B-C-GMR PDF预览

SI5326B-C-GMR

更新时间: 2024-11-19 20:10:55
品牌 Logo 应用领域
芯科 - SILICON 外围集成电路
页数 文件大小 规格书
72页 1660K
描述
Processor Specific Clock Generator, QFN-36

SI5326B-C-GMR 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:QFN-36
针数:36Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2.29
JESD-30 代码:S-XQCC-N36长度:6 mm
湿度敏感等级:2端子数量:36
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:0.9 mm表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

SI5326B-C-GMR 数据手册

 浏览型号SI5326B-C-GMR的Datasheet PDF文件第2页浏览型号SI5326B-C-GMR的Datasheet PDF文件第3页浏览型号SI5326B-C-GMR的Datasheet PDF文件第4页浏览型号SI5326B-C-GMR的Datasheet PDF文件第5页浏览型号SI5326B-C-GMR的Datasheet PDF文件第6页浏览型号SI5326B-C-GMR的Datasheet PDF文件第7页 
Si5326  
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER  
ATTENUATOR  
Features  
Generates any frequency from 2 kHz Dual clock outputs with selectable  
to 945 MHz and select frequencies to  
1.4 GHz from an input frequency of  
2 kHz to 710 MHz  
Ultra-low jitter clock outputs with jitter  
generation as low as 0.3 ps rms  
(50 kHz–80 MHz)  
Integrated loop filter with selectable  
loop bandwidth (60 Hz to 8.4 kHz)  
Meets OC-192 GR-253-CORE jitter  
specifications  
Dual clock inputs with manual or  
automatically controlled hitless  
switching (LVPECL, LVDS, CML,  
CMOS)  
signal format  
Support for ITU G.709 and custom  
FEC ratios (255/238, 255/237,  
255/236)  
LOL, LOS, FOS alarm outputs  
Digitally-controlled output phase  
adjustment  
I2C or SPI programmable  
On-chip voltage regulator for  
1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%  
operation  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS compliant  
Ordering Information:  
See page 65.  
Pin Assignments  
Applications  
SONET/SDH OC-48/OC-192/STM-  
16/STM-64 line cards  
ITU G.709 and custom FEC line  
cards  
GbE/10GbE, 1/2/4/8/10G Fibre  
Channel line cards  
GbE/10GbE Synchronous Ethernet  
Optical modules  
36 35 34 33 32 31 30 29 28  
Wireless basestations  
Data converter clocking  
xDSL  
PDH clock synthesis  
Test and measurement  
Broadcast video  
RST  
NC  
1
2
3
4
5
6
7
8
9
27 SDI  
26  
A2_SS  
25 A1  
INT_C1B  
C2B  
24  
23  
A0  
GND  
Pad  
VDD  
XA  
SDA_SDO  
22 SCL  
XB  
21  
20  
19  
CS_CA  
INC  
GND  
NC  
DEC  
10 11 12 13 14 15 16 17 18  
Description  
The Si5326 is a jitter-attenuating precision clock multiplier for applications  
requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging  
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to  
945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down  
separately from a common source. The Si5326 can also use its crystal oscillator  
as a clock source for frequency synthesis. The device provides virtually any  
frequency translation combination across this operating range. The Si5326 input  
clock frequency and clock multiplication ratio are programmable through an I2C or  
SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation  
DSPLL® technology, which provides frequency synthesis and jitter attenuation in a  
highly integrated PLL solution that eliminates the need for external VCXO and  
loop filter components. The DSPLL loop bandwidth is digitally programmable,  
providing jitter performance optimization at the application level. Operating from a  
single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock  
multiplication and jitter attenuation in high performance timing applications.  
Rev. 1.0 9/10  
Copyright © 2010 by Silicon Laboratories  
Si5326  

SI5326B-C-GMR 替代型号

型号 品牌 替代类型 描述 数据表
SI5326C-C-GM SILICON

完全替代

ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5326B-C-GM SILICON

完全替代

ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Si5326A-C-GM SILICON

完全替代

ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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