Preliminary PLL103-03
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS
FEATURES
PIN CONFIGURATION
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Generates 24-output buffers from one input.
Supports up to 4 DDR DIMMS or 3 SDR DIMMS
and 2 DDR DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V or 3.3V Supply range.
FBOUT
VDD3.3_2.5
1
2
3
4
5
6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR
VDD2.5
GND
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
VDD3.3_2.5
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
·
·
·
·
·
·
7
8
GND
9
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DDR9T
DDR9C
VDD2.5
PD#
Enhanced DDR and SDRAM Output Drive
selected by I2C.
Available in 48 pin SSOP.
BUF_IN
GND
DDR3T_SDRAM4
GND
DDR8T
DDR8C
VDD2.5
GND
·
DDR3C_SDRAM5
VDD3.3_2.5
GND
BLOCK DIAGRAM
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
DDR7T
DDR7C
DDR6T
DDR6C
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR6T
SDATA
SCLK
SDATA
I2C
Control
SCLK
Note: #: Active Low
DESCRIPTIONS
The PLL103-03 is designed as a 3.3V/2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR (Double
Data Rate) DIMMS or to support 2 unbuffered
standard SDR (Single Data Rate) DIMMS and 2 DDR
DIMMS. The PLL103-03 can be used in conjunction
with the PLL202-04 or similar clock synthesizer for
the VIA Pro 266 chipset.
BUF_IN
DDR6C
DDR7T
DDR7C
DDR8T
The PLL103-03 also has an I2C interface, which can
enable or disable each output clock. When power up,
all output clocks are enabled (has internal pull up).
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
PD#
FBOUT
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 08/28/00 Page 1