Datasheet > PLL103-05

PLL103-05

更新时间： 2024-11-08 10:08:39

品牌	Logo	应用领域
PLL		时钟
页数	文件大小	规格书
4页	119K
描述
1-to-5 Clock Distribution Buffer

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数据手册

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PLL103-05 数据手册

Preliminary PLL103-05

1-to-5 Clock Distribution Buffer

FEATURES

PIN CONFIGURATION

5 outputs identical to FIN.

FIN

CLK1

CLK2

CLK3

CLK5

VDD

Low skew (< 250 ps between outputs).

Input / Output frequency range 0 – 160 MHz

25mA drive capability at TTL levels.

70mA drive capability at CMOS levels.

3.3V operation.

GND

CLK4

Available in 8-Pin 150mil SOIC.

FIN = 0 ~ 160 Mhz

DESCRIPTIONS

The PLL103-05 is a 1-to-5 Clock Distribution Buffer,

reproducing the reference input frequency (FIN) at 5

different outputs. It is designed to minimize skew

between outputs and provides TTL and CMOS

compatible output levels.

BLOCK DIAGRAM

CLK1

CLK2

CLK3

CLK4

CLK5

FIN

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 09/26/00 Page 1

12 3 4

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与PLL103-05相关器件

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