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PLL103-53XM PDF预览

PLL103-53XM

更新时间: 2024-09-21 10:08:39
品牌 Logo 应用领域
PLL 动态存储器双倍数据速率
页数 文件大小 规格书
7页 145K
描述
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

PLL103-53XM 数据手册

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Preliminary PLL103-53  
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS  
FEATURES  
PIN CONFIGURATION  
·
·
Generates 30-output buffers from one input.  
Supports up to 4 DDR DIMMS or 3 SDR DIMMS  
and 2 DDR DIMMS.  
Supports 266MHz DDR SDRAM.  
One additional output for feedback.  
Less than 5ns delay.  
Skew between any outputs is less than 100 ps.  
2.5V or 3.3V Supply range.  
FBOUT  
VDD3.3_2.5  
1
2
3
4
5
6
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
SEL_DDR  
VDD2.5  
GND  
GND  
DDR0T_SDRAM10  
DDR0C_SDRAM11  
DDR1T_SDRAM0  
DDR1C_SDRAM1  
VDD3.3_2.5  
DDR11T  
DDR11C  
DDR10T  
DDR10C  
VDD2.5  
GND  
·
·
·
·
·
·
7
8
9
GND  
DDR2T_SDRAM2  
DDR2C_SDRAM3  
VDD3.3_2.5  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DDR9T  
DDR9C  
VDD2.5  
PD#  
Enhanced DDR and SDRAM Output Drive  
selected by I2C.  
Available in 56 pin SSOP.  
BUF_IN  
GND  
DDR3T_SDRAM4  
GND  
DDR8T  
DDR8C  
VDD2.5  
GND  
·
DDR3C_SDRAM5  
VDD3.3_2.5  
GND  
DDR4T_SDRAM6  
DDR4C_SDRAM7  
DDR5T_SDRAM8  
DDR5C_SDRAM9  
VDD3.3_2.5  
SDATA  
DDR7T  
DDR7C  
DDR6T  
DDR6C  
GND  
SCLK  
GND  
VDD2.5  
GND  
VDD2.5  
DDR12T  
DDR13C  
DDR13T  
DDR12C  
Note: #: Active Low  
DESCRIPTIONS  
BLOCK DIAGRAM  
The PLL103-53 is designed as a 3.3V/2.5V buffer to  
distribute high-speed clocks in PC applications. The  
device has 30 outputs. These outputs can be  
configured to support 4 unbuffered DDR (Double  
Data Rate) DIMMS or to support 3 unbuffered  
standard SDR (Single Data Rate) DIMMS and 2 DDR  
DIMMS. The PLL103-53 can be used in conjunction  
with the PLL202-14/-54 or similar clock synthesizer  
for the VIA Pro 266 chipset.  
DDR0T_SDRAM10  
DDR0C_SDRAM11  
DDR1T_SDRAM0  
DDR1C_SDRAM1  
DDR2T_SDRAM2  
DDR2C_SDRAM3  
DDR3T_SDRAM4  
DDR3C_SDRAM5  
DDR4T_SDRAM6  
DDR4C_SDRAM7  
DDR5T_SDRAM8  
DDR5C_SDRAM9  
DDR(6:13)T  
I2C  
SDATA  
SCLK  
Control  
The PLL103-53 also has an I2C interface, which can  
enable or disable each output clock. When power up,  
all output clocks are enabled (has internal pull up).  
BUF_IN  
DDR(6:13)C  
FBOUT  
PD#  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 12/01/00 Page 1  

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