Datasheet > PLL103-11

PLL103-11

更新时间： 2024-11-25 10:08:39

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
7页	144K
描述
Low Skew Buffers

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数据手册

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PLL103-11 数据手册

PLL103-11

Low Skew Buffers

FEATURES

PIN CONFIGURATION

Generates 13 copies of High-speed clock inputs.

Supports up to three SDRAM DIMMS synchronous

clocks.

Supports 2-wire I2C serial bus interface with

readback.

50% duty cycle with low jitter.

Less than 5ns delay.

Skew between any outputs is less than 250 ps.

Tri-state pin for testing.

Frequency up to 150 MHz.

3.0V-3.7V Supply range.

Available in 28-pin 300mil SOIC package.

VDD

SDRAM0

SDRAM1

GND

VDD

SDRAM11

SDRAM10

GND

VDD

SDRAM2

SDRAM3

GND

SDRAM9

SDRAM8

GND

BUF_IN

SDRAM4

SDRAM5

SDRAM12

VDD1

VDD

SDRAM7

SDRAM6

GND

GND1

SDATA

SCLK

BLOCK DIAGRAM

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

SDRAM7

SDRAM8

SDRAM9

SDRAM10

SDRAM11

SDRAM12

I2C

SDATA

SCLK

POWER GROUP

Control

VDD: SDRAM (0:12)

VDD1: I2C Circuitry

GROUND GROUP

GND: SDRAM (0:12)

GND1: I2C Circuitry

BUF_IN

KEY SPECIFICATIONS

BUF_IN to SDRAM outputs Delay: 1 ~ 5 ns.

Output Slew: ³ 1.5 V/ns.

Output Skew: ±250 ps.

Output Duty Cycle: 50% ± 5%.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 11/07/00 Page 1

12 3 4 5 6 7

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