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PLL103-06XM PDF预览

PLL103-06XM

更新时间: 2024-11-08 10:08:39
品牌 Logo 应用领域
PLL 动态存储器双倍数据速率
页数 文件大小 规格书
7页 143K
描述
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

PLL103-06XM 数据手册

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Preliminary PLL103-06  
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS  
FEATURES  
PIN CONFIGURATION  
·
·
Generates 12-output buffers from one input.  
Supports up to 2 DDR DIMMS or 3 SDRAM  
DIMMS.  
Supports 266MHz DDR SDRAM.  
One additional output for feedback.  
Less than 5ns delay.  
Skew between any outputs is less than 100 ps.  
2.5V or 3.3V Supply range.  
FBOUT  
PD#  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SEL_DDR  
DDR5T_SDRAM10  
DDR5C_SDRAM11  
VDD3.3_2.5  
GND  
DDR0T_SDRAM0  
DDR0C_SDRAM1  
VDD3.3_2.5  
GND  
3
·
·
·
·
·
·
4
5
6
DDR4T_SDRAM8  
DDR4C_SDRAM9  
VDD3.3_2.5  
GND  
DDR1T_SDRAM2  
DDR1C_SDRAM3  
VDD3.3_2.5  
BUF_IN  
7
8
Enhanced DDR and SDRAM Output Drive  
selected by I2C.  
Available in 28 pin SSOP.  
9
10  
11  
12  
13  
14  
DDR3T_SDRAM6  
DDR3C_SDRAM7  
GND  
·
GND  
DDR2T_SDRAM4  
DDR2C_SDRAM5  
VDD3.3_2.5  
BLOCK DIAGRAM  
SCLK  
SDATA  
Note: #: Active Low  
DDR0T_SDRAM0  
DDR0C_SDRAM1  
DDR1T_SDRAM2  
DDR1C_SDRAM3  
DDR2T_SDRAM4  
DDR2C_SDRAM5  
DDR3T_SDRAM6  
DDR3C_SDRAM7  
DDR4T_SDRAM8  
DDR4C_SDRAM9  
DDR5T_SDRAM10  
DDR5C_SDRAM11  
SDATA  
I2C  
SCLK  
Control  
PD#  
DESCRIPTIONS  
The PLL103-06 is designed as a 3.3V/2.5V buffer to  
distribute high-speed clocks in PC applications. The  
device has 12 outputs. These outputs can be  
configured to support 3 unbuffered standard SDR  
(Single Data Rate) DIMMS and 2 DDR DIMMS. The  
PLL103-06 can be used in conjunction with the  
PLL202-04 or similar clock synthesizer for the VIA  
Pro 266 chipset.  
BUF_IN  
FBOUT  
The PLL103-06 also has an I2C interface, which can  
enable or disable each output clock. When power up,  
all output clocks are enabled (has internal pull up).  
SEL_DDR  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 12/20/00 Page 1  

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