Datasheet > PLL103-07XM

PLL103-07XM

更新时间： 2024-09-21 10:08:39

品牌	Logo	应用领域
PLL		双倍数据速率
页数	文件大小	规格书
7页	141K
描述
2 DIMM DDR Fanout Buffer

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中文翻译

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数据手册

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PLL103-07XM 数据手册

Preliminary PLL103-07

2 DIMM DDR Fanout Buffer

FEATURES

PIN CONFIGURATION

Generates 12-output buffers from one input.

FBOUT

GND

Supports VIA Pro266 DDR chipset.

Supports up to 2 DDR DIMMS.

Supports up to 400MHz DDR, SDRAMS.

One additional output for feedback.

6 differential clock distribution.

Less than 5ns delay.

Skew between any outputs is less than 100 ps.

2.5V Supply range.

Available in 28-pin SSOP.

DDRT5

DDRC5

VDD2.5

GND

DDRT0

DDRC0

VDD2.5

GND

DDRT4

DDRC4

VDD2.5

GND

DDRT1

DDRC1

VDD2.5

BUF_IN

GND

DDRT3

DDRC3

VDD2.5

SCLK

BLOCK DIAGRAM

DDRT2

DDRC2

VDD2.5

SDATA

Note: #: Active Low

DDR0T

DDR0C

DDR1T

DDR1C

DDR2T

DDR2C

DDR3T

DDR3C

DDR4T

DDR4C

DDR5T

DDR5C

SDATA

I2C

Control

SCLK

DESCRIPTIONS

The PLL103-07 is designed as a 2.5V buffer to

distribute high-speed clocks in PC applications. The

device has 12 outputs. These outputs can be

configured to support 2 DDR DIMMs. The PLL103-07

can be used in conjunction with the PLL202-04 or

similar clock synthesizer for the VIA Pro 266 chipset.

BUF_IN

FBOUT

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 01/03/01 Page 1

12 3 4 5 6 7

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