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PLL103-04SC PDF预览

PLL103-04SC

更新时间: 2024-11-08 10:08:39
品牌 Logo 应用领域
PLL 时钟
页数 文件大小 规格书
4页 119K
描述
1-to-4 Clock Distribution Buffer

PLL103-04SC 数据手册

 浏览型号PLL103-04SC的Datasheet PDF文件第2页浏览型号PLL103-04SC的Datasheet PDF文件第3页浏览型号PLL103-04SC的Datasheet PDF文件第4页 
Preliminary PLL103-04  
1-to-4 Clock Distribution Buffer  
FEATURES  
PIN CONFIGURATION  
·
·
·
·
·
·
4 outputs identical to FIN.  
FIN  
CLK1  
CLK2  
CLK3  
OE^  
1
2
3
4
8
7
6
5
Low skew (< 250 ps between outputs).  
Input / Output frequency range 0 – 160 MHz  
25mA drive capability at TTL levels.  
70mA drive capability at CMOS levels.  
Output enable mode available to tri-state all  
outputs.  
VDD  
GND  
CLK4  
·
·
3.3V operation.  
Available in 8-Pin 150mil SOIC.  
FIN = 0 ~ 160 Mhz  
Note: ^: Internal pull-up (30kW)  
DESCRIPTIONS  
The PLL103-04 is a 1-to-4 Clock Distribution Buffer,  
reproducing the reference input frequency (FIN) at 4  
different outputs. It is designed to minimize skew  
between outputs and provides TTL and CMOS  
compatible output levels. An output enable selector is  
available to tri-state all outputs.  
BLOCK DIAGRAM  
OE^  
CLK1  
CLK2  
CLK3  
CLK4  
FIN  
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991  
Rev 09/26/00 Page 1  

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