Datasheet > PLL103-01XM

PLL103-01XM

更新时间： 2024-11-08 06:04:07

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
7页	67K
描述
Low Skew Buffers

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中文翻译

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数据手册

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PLL103-01XM 数据手册

PLL103-01

Low Skew Buffers

FEATURES

PIN CONFIGURATION

Generate 18 copies of High-speed clock inputs.

Supports up to four SDRAM DIMMS synchronous

clocks.

Supports 2-wire I2C serial bus interface with

readback.

50% duty cycle with low jitter.

Less than 5ns delay.

Skew between any outputs is less than 250 ps.

Tri-state pin for testing.

Frequency up to 133 MHZ.

3.0V-3.7V Supply range.

N/C

VDD

SDRAM15

SDRAM14

GND

SDRAM0

SDRAM1

GND

VDD

SDRAM13

SDRAM12

GND

SDRAM2

SDRAM3

GND

OE^

BUF_IN

VDD

SDRAM4

SDRAM11

SDRAM10

GND

SDRAM5

GND

VDD

48-pin SSOP package.

SDRAM9

SDRAM8

GND

SDRAM6

SDRAM7

GND

VDD

BLOCK DIAGRAM

SDRAM17

GND

SDRAM16

GND

GND1

VDD1

SCLK

SDATA

Note: ^: pull up

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM4

SDRAM5

SDRAM6

SDRAM7

SDRAM8

SDRAM9

SDRAM10

SDRAM11

SDRAM12

SDRAM13

SDRAM14

SDRAM15

SDRAM16

SDRAM17

SDATA

I2C

Control

SCLK

POWER GROUP

VDD: SDRAM( 0:17 )

VDD1: I2C Circuitry

GROUND GROUP

GND: SDRAM( 0:17 )

GND1: I2C Circuitry

BUF_IN

KEY SPECIFICATIONS

BUFIN to SDRAM outputs Delay: 1 ~ 5 ns.

Output Slew: ³ 1.5 V/ns.

Output Skew: ±250 ps.

Output Duty Cycle: 50% ± 5%.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/08/00 Page 1

12 3 4 5 6 7

中文翻译

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