Datasheet > PLL103-02XC-R

PLL103-02XC-R

更新时间： 2024-11-08 07:03:39

品牌	Logo	应用领域
PLL		动态存储器双倍数据速率 PC
页数	文件大小	规格书
6页	179K
描述
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

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数据手册

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PLL103-02XC-R 数据手册

PLL103-02

DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS

FEATURES

PIN CONFIGURATION

•

Generates 24 output buffers from one input.

FBOUT

VDD2.5

GND

DDR0T

DDR0C

DDR1T

DDR1C

VDD2.5

GND

DDR2T

DDR2C

VDD2.5

BUF_IN

N/C

VDD2.5

GND

Supports up to four DDR DIMMS.

Supports 266MHz DDR SDRAM.

One additional output for feedback.

Less than 5ns delay.

Skew between any outputs is less than 100 ps.

2.5V Supply range.

DDR11T

DDR11C

DDR10T

DDR10C

VDD2.5

GND

DDR9T

DDR9C

VDD2.5

PD#

Enhanced DDR Output Drive selected by I2C.

Available in 48 pin SSOP.

BLOCK DIAGRAM

DDR0T

DDR0C

DDR1T

DDR1C

DDR2T

DDR2C

DDR3T

DDR3C

DDR4T

DDR4C

DDR5T

DDR5C

DDR6T

DDR6C

DDR7T

DDR7C

DDR8T

DDR8C

DDR9T

DDR9C

DDR10T

DDR10C

DDR11T

DDR11C

GND

DDR3T

GND

SDATA

I2C

DDR8T

DDR8C

VDD2.5

GND

DDR7T

DDR7C

DDR6T

DDR6C

GND

Control

SCLK

DDR3C

VDD2.5

GND

DDR4T

DDR4C

DDR5T

DDR5C

VDD2.5

SDATA

BUF_IN

SCLK

Note: #: Active Low

DESCRIPTION

The PLL103-02 is designed as a 2.5V buffer to

distribute high-speed clocks in PC applications. The

device has 24 outputs. These outputs can be

configured to support four unbuffered DDR DIMMS.

The PLL103-02 can be used in conjunction with a

clock synthesizer for the VIA Pro 266 chipset.

The PLL103-02 also has an I2C interface, which can

enable or disable each output clock. When powered

up, all output clocks are enabled (have internal pull

ups).

PD#

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

12 3 4 5 6

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与PLL103-02XC-R相关器件

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