Datasheet > PLL102-108XI

PLL102-108XI

更新时间： 2024-11-10 10:08:39

品牌	Logo	应用领域
PLL		时钟驱动器双倍数据速率
页数	文件大小	规格书
10页	162K
描述
Programmable DDR Zero Delay Clock Driver

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数据手册

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PLL102-108XI 数据手册

PLL102-108

Programmable DDR Zero Delay Clock Driver

FEATURES

PIN CONFIGURATION

PLL clock distribution optimized for Double Data

GND

CLKC0

CLKT0

VDD

GND

Rate SDRAM application up to 266Mhz.

Distributes one clock Input to one bank of ten

differential outputs.

CLKC5

CLKT5

VDD

CLKT1

CLKC1

GND

CLKT6

CLKC6

GND

Track spread spectrum clocking for EMI reduction.

Programmable delay between CLK_INT and

CLK[T/C] from –0.8ns to +3.1ns by programming

CLKINT and FBOUT skew channel, or from –1.1ns to

+3.5ns if additional DDR skew channels are enabled.

Four independent programmable DDR skew chan-

nels from –0.3ns to +0.4ns with step size ±100ps.

Support 2-wire I2C serial bus interface.

2.5V Operating Voltage.

GND

CLKC2

CLKT2

VDD

CLKC7

CLKT7

VDD

SCLK

CLK_INT

N/C

SDATA

N/C

FB_INT

VDD

AVDD

AGND

GND

FB_OUTT

N/C

GND

Available in 48-Pin 300mil SSOP.

CLKC3

CLKT3

VDD

CLKC8

CLKT8

VDD

DESCRIPTIONS

CLKT4

CLKC4

GND

CLKT9

CLKC9

GND

The PLL102-108 is a zero delay buffer that distributes

a single-ended clock input to ten pairs of differential

clock outputs and one feedback clock output. Output

signal duty cycles are adjusted to 50%, independent of

the duty cycle at CLK_INT. The PLL can be bypassed

for test purposes by strapping AV_ddto ground.

BLOCK DIAGRAM

Programmable

Skew Channel

Control

Logic

-600~+800ps

±200ps step

AV_DD

FB_OUTT

CLKT0

CLKC0

CLKT1

CLKC1

CLKT5

CLKC5

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

Programmable

Delay Channel

-300~+400ps

±100ps step

(0~2.5ns)

+170ps step

CLK_INT

PLL

-300~+400ps

±100ps step

FB_INT

AV_DD

-300~+400ps

±100ps step

-300~+400ps

±100ps step

CLKT6

CLKC6

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/29/02 Page 1

12 3 4 5 6 7...10

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与PLL102-108XI相关器件

型号	品牌	获取价格	描述	数据表
PLL102-108XM	PLL	获取价格	Programmable DDR Zero Delay Clock Driver
PLL102-109	PLL	获取价格	Programmable DDR Zero Delay Clock Driver
PLL102-109XC	PLL	获取价格	Programmable DDR Zero Delay Clock Driver
PLL102-109XI	PLL	获取价格	Programmable DDR Zero Delay Clock Driver
PLL102-109XM	PLL	获取价格	Programmable DDR Zero Delay Clock Driver
PLL102-10SC	PLL	获取价格	Low Skew Output Buffer
PLL102-10SC-R	PLL	获取价格	Low Skew Output Buffer
PLL102-15	PLL	获取价格	Low Skew Output Buffer
PLL102-15SC	PLL	获取价格	Low Skew Output Buffer
PLL103-01	PLL	获取价格	Low Skew Buffers