Datasheet > PLL102-10SC-R

PLL102-10SC-R

更新时间： 2024-11-10 10:08:39

品牌	Logo	应用领域
PLL		/
页数	文件大小	规格书
6页	180K
描述
Low Skew Output Buffer

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数据手册

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PLL102-10SC-R 数据手册

PLL102-10

Low Skew Output Buffer

FEATURES

PIN CONFIGURATION

•

Frequency range 50 ~ 120MHz.

Internal phase locked loop will allow spread spec-

trum modulation on reference clock to pass to out-

puts.

REFIN

GND

CLKOUT

DNC

•

Zero input - output delay.

Less than 700 ps device - device skew.

Less than 250 ps skew between outputs.

Less than 100 ps cycle - cycle jitter.

2.5V or 3.3V power supply operation.

Available in 8-Pin SOIC or MSOP package.

CLK1

CLK2

DNC

VDD

DESCRIPTION

The PLL102-10 is a high performance, low skew, low

jitter zero delay buffer designed to distribute high

speed clocks and is available in 8-pin SOIC or MSOP

package. It has two outputs that are synchronized with

the input. The synchronization is established via

CLKOUT feed back to the input of the PLL. Since the

skew between the input and output is less than ±350

ps, the device acts as a zero delay buffer.

BLOCK DIAGRAM

REFIN

CLKOUT

CLK1

PLL

CLK2

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/22/05 Page 1

12 3 4 5 6

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