Datasheet > PLL102-109XC

PLL102-109XC

更新时间： 2024-11-08 06:04:07

品牌	Logo	应用领域
PLL		时钟驱动器双倍数据速率
页数	文件大小	规格书
10页	163K
描述
Programmable DDR Zero Delay Clock Driver

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PLL102-109XC 数据手册

Preliminary PLL102-109

Programmable DDR Zero Delay Clock Driver

FEATURES

PIN CONFIGURATION

PLL clock distribution optimized for Double Data

Rate SDRAM application up to 266Mhz.

Distributes one clock Input to one bank of six

differential outputs.

Track spread spectrum clocking for EMI reduction.

Programmable delay between CLK_INT and CLK[T/C]

from –0.8ns to +3.1ns by programming CLKINT and

FBOUT skew channel, or from –1.1ns to +3.5ns if

additional DDR skew channels are enabled.

Two independent programmable DDR skew chan-

nels from –0.3ns to +0.4ns with step size ±100ps.

CLKCO

CLKT0

VDD

GND

CLKC5

CLKT5

CLKC4

CLKT4

VDD

CLKT1

CLKC1

GND

SCLK

CLK_INT

N/C

SDATA

N/C

FB_INT

FB_OUTT

ADDR_SEL

CLKT3

CLKC3

GND

AVDD

AGND

VDD

CLKT2

CLKC2

Support 2-wire I C serial bus interface.

2.5V Operating Voltage.

Available in 28-Pin 209mil SSOP.

DESCRIPTIONS

The PLL102-109 is a zero delay buffer that distributes

a single-ended clock input to six pairs of differential

clock outputs and one feedback clock output. Output

signal duty cycles are adjusted to 50%, independent of

the duty cycle at CLK_INT. The PLL can be bypassed

for test purposes by strapping AV_DDto ground.

BLOCK DIAGRAM

Programmable

Skew Channel

-600~+800ps

±200ps step

FB_OUTT

Control

Logic

AV_DD

CLKT0

CLKC0

CLKT1

CLKC1

CLKT5

CLKC5

-300~+400ps

±100ps step

Programmable

Delay Channel

(0~2.5ns)

+170ps step