Datasheet > PI74ALVCH32245NB

PI74ALVCH32245NB

更新时间： 2024-10-26 23:27:39

品牌	Logo	应用领域
其他 - ETC		总线收发器逻辑集成电路
页数	文件大小	规格书
7页	161K
描述
Quad 8-bit Bus Transceiver

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PI74ALVCH32245NB 数据手册

PI74ALVCH32245

3.3V, 32-Bit Bidirectional Transceiver

with 3-State Outputs

Product Features

Product Description

Pericom Semiconductors PI74ALVCH series of logic circuits are

produced using the Companys advanced 0.5 micron CMOS

technology, achieving industry leading speed grades.

• PI74ALVCH32245 is designed for low voltage operation

• V = 2.3V to 3.6V

• Typical V

(Output Ground Bounce)

OLP

The PI74ALVCH32245 is a 32-bit bidirectional transceiver

designed for asynchronous two-way communication between

data buses. The direction control input pin (xDIR) determines

the direction of data flow through the bidirectional transceiver.

The Direction and Output Enable controls are designed to operate

thisdeviceaseitherfourindependent8-bittransceivers,two16-Bit

transceivers, or one 32-Bit transceiver. The output enable (OE)

input, when HIGH, disables both A and B ports by placing them in

HIGHZcondition.

< 0.8V at V = 3.3V, T = 25°C

• Typical V

(Output V Undershoot)

OHV

> 2.0V atV = 3.3V, T = 25°C

• Bus Hold retains last active bus state during 3-State,

eliminating the need for external pullup resistors

• Industrial operation at 40°C to +85°C

• Packages available:

96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine

pitch ball grid array, LFBGA(NB)

To ensure the high-impedance state during power up or power

down, OE should be tied to V through a pull-up resistor; the

minimum value of the resistor is determined by the current sinking

ability of the driver.

Active bus-hold circuitry is provided to hold unused or floating

data inputs at a valid logic level.

Logic Block Diagram (Positive Logic)

1DIR

2DIR

1OE

1B1

2OE

1A1

2A1

2B1

To Seven Other Channels

3DIR

3A1

4DIR

3OE

3B1

4OE

4A1

4B1

To Seven Other Channels

PS8437

08/24/01

12 3 4 5 6 7

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