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PI74ALVCHR16269VEX PDF预览

PI74ALVCHR16269VEX

更新时间: 2024-10-27 15:47:55
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管逻辑集成电路
页数 文件大小 规格书
5页 351K
描述
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLASTIC, SSOP-56

PI74ALVCHR16269VEX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.63
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
长度:18.415 mm逻辑集成电路类型:BUS EXCHANGER
位数:12功能数量:1
端口数量:3端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):245传播延迟(tpd):7.7 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmBase Number Matches:1

PI74ALVCHR16269VEX 数据手册

 浏览型号PI74ALVCHR16269VEX的Datasheet PDF文件第2页浏览型号PI74ALVCHR16269VEX的Datasheet PDF文件第3页浏览型号PI74ALVCHR16269VEX的Datasheet PDF文件第4页浏览型号PI74ALVCHR16269VEX的Datasheet PDF文件第5页 
PI74ALVCHR16269  
12-Bit to 24-Bit Registered Bus Exchanger  
with 3-State Outputs  
ProductDescription  
Product Features  
Pericom Semiconductor’s PI74ALVCH series of logic circuits are  
produced using the Company’s advanced 0.5 micron CMOS  
technology, achieving industry leading speed.  
· PI74ALVCHR16269 is designed for low voltage operation  
· V = 2.3V to 3.6V  
CC  
· Hysteresis on all inputs  
The PI7ALVCHR16269isusedinapplicationsinwhichtwoseparate  
portsmustbemultiplexedonto,ordemultiplexedfrom,asingleport.It  
isparticularlysuitableasaninterfacebetweensynchronousDRAM’s  
and high-speed microprocessors.  
· Typical V  
(Output Ground Bounce)  
OLP  
< 0.8V atV = 3.3V, T = 25°C  
CC  
A
· Typical V  
(Output V Undershoot)  
OH  
OHV  
< 2.0V atV = 3.3V, T = 25°C  
CC  
A
Data is stored on the internal B-port registers on the low-to-high  
transitionoftheclock(CLK)inputwhentheappropriateclock-enable  
(CLKENA) inputs are low. Proper control of these inputs allows two  
sequential12-bitwordstobepresentedasa24-bitwordontheB-port.  
For data transfer in the B-to-A direction, a single storage register is  
provided.Theselect(SEL)lineselects1Bor2BdatafortheAoutputs.  
The register on the A output permits the fastest possible data transfer,  
thusextendingtheperiodduringwhichthedataisvalidonthebus.The  
controlterminalsareregisteredsothatalltransactionsaresynchronous  
with CLK. Data flow is controlled by the active-low output enables  
(OEA,OEB1,andOEB2).  
· All output ports have equivalent 26W series resistors,  
no external resistors are required  
· Bus Hold retains last active bus state during 3-State,  
eliminating the need for external pullup resistors  
· Industrial operation at –40°C to +85°C  
· Packages available:  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 300 mil wide plastic SSOP (V)  
Toensurethehigh-impedancestateduringpoweruporpowerdown,  
a clock pulse should be applied as soon as possible and OE should  
LogicBlockDiagram  
be tied to V through a pullup resistor; the minimum value of the  
CC  
resistorisdeterminedbythecurrent-sinkingcapabilityofthedriver.  
Due to OE being routed through a register, the active state of the  
outputs cannot be determined prior to the arrival of the first clock  
pulse.  
Activebus-holdcircuitryisprovidedtoholdunusedorfloatingdata  
inputs at a valid logic level.  
All outputs are designed to sink up to 12mA and include 26-ohm  
resistors to reduce overshoot and undershoot.  
PS8372  
12/17/99  
1

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