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PI74ALVTC16240K PDF预览

PI74ALVTC16240K

更新时间: 2024-10-26 23:27:39
品牌 Logo 应用领域
百利通 - PERICOM 驱动器
页数 文件大小 规格书
8页 347K
描述
Quad 4-Bit Buffer/Driver

PI74ALVTC16240K 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP, TSSOP48,.25,16
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92控制类型:ENABLE LOW
系列:ALVTJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:9.7 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.25,16封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:2.6 ns
传播延迟(tpd):3.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm

PI74ALVTC16240K 数据手册

 浏览型号PI74ALVTC16240K的Datasheet PDF文件第2页浏览型号PI74ALVTC16240K的Datasheet PDF文件第3页浏览型号PI74ALVTC16240K的Datasheet PDF文件第4页浏览型号PI74ALVTC16240K的Datasheet PDF文件第5页浏览型号PI74ALVTC16240K的Datasheet PDF文件第6页浏览型号PI74ALVTC16240K的Datasheet PDF文件第7页 
PI74ALVTC16240  
16-Bit Buffer/Driver  
with 3-State Outputs  
Product Features  
Product Description  
• PI74ALVTCfamilyisdesignedforlowvoltageoperation,  
Pericom Semiconductor’s PI74ALVTC series of logic circuits are  
produced in the Company’s advanced 0.35 micron CMOS tech-  
nology, achieving industry leading speed.  
VDD = 1.8V to 3.6V  
• Supports Live Insertion  
The PI74ALVTC16240 buffer/driver is designed specifically to  
improve both the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and  
transmitters.  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• High Drive, -32/64mA @ 3.3V  
• Uses patented noise reduction circuitry  
• Power-off high impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packages available:  
The device can be used as four 4-bit buffers, two 8-bit buffers, or  
one 16-bit buffer. It provides inverting outputs and symmetrical  
active-low output-enable (OE) inputs.  
To ensure the high-impedance state during power up or power  
down, OE should be tied to Vdd through a pullup resistor; the  
minimum value of the resistor is determined by the current-sink-  
ing capability of the driver.  
–48-pin240milwideplasticTSSOP(A)  
–48-pin173milwideplasticTVSOP(K)  
–48-pin300milwideplasticSSOP(V)  
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state whenever the data input goes to high-impedance,  
preventing “floating” inputs and eliminating the need for pullup/  
down resistors.  
Logic Block Diagram  
PS8353A  
11/23/98  
1

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