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PI74ALVCHT16835VE PDF预览

PI74ALVCHT16835VE

更新时间: 2024-10-27 14:44:11
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 132K
描述
Bus Driver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLASTIC, SSOP-56

PI74ALVCHT16835VE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
长度:18.415 mm逻辑集成电路类型:BUS DRIVER
位数:18功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):5.6 ns
认证状态:Not Qualified座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

PI74ALVCHT16835VE 数据手册

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PI74ALVCHT16835  
18-Bit Universal Bus Driver  
with 3-State Outputs  
Product Description  
Product Features  
Pericom Semiconductor’s PI74ALVCH series of logic circuits are  
produced using the Company’s advanced 0.5 micron CMOS  
technology, achieving industry leading speed.  
PI74ALVCHT16835 is designed for low-voltage operation  
V = 2.3V to 3.6V  
CC  
5V I/O Tolerant Inputs and Outputs  
The 18-bit PI74ALVCHT16835 universal bus driver is designed  
for 2.3V to 3.6V VCC operation.  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8V at V = 3.3V, T = 25°C  
CC  
A
Data flow from A to Y is controlled by Output Enable (OE). The  
device operates in the transparent mode when LE is HIGH. The A  
data is latched if CLK is held at a high or low logic level. If LE is  
LOW, the A-bus is stored in the latch/flip-flop on the low-to-high  
transition of CLK. When OE is HIGH, the outputs are in the high-  
impedance state.  
Typical V  
(Output V Undershoot)  
OH  
OHV  
< 2.0V at V = 3.3V, T = 25°C  
CC  
A
Bus Hold retains last active bus state during 3-State,  
eliminating the need for external pullup resistors  
Industrial operation at –40°C to +85°C  
Packages available:  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pullup resistor; the  
minimum value of the resistor is determined by the current-sinking  
capability of the driver.  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 300 mil wide plastic SSOP (V)  
– 56-pin 173 mil wide plastic TVSOP (K)  
Activebus-holdcircuitryisprovidedtoholdunusedorfloatingdata  
inputs at a valid logic level.  
Logic Block Diagram  
27  
OE  
30  
CLK  
28  
LE  
54  
A1  
1D  
C1  
CLK  
3
Y1  
TO 17 OTHER CHANNELS  
PS8547C  
12/12/01  
1

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