PI74ALVCHR16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
ProductDescription
Product Features
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
· PI74ALVCHR16269 is designed for low voltage operation
· V = 2.3V to 3.6V
CC
· Hysteresis on all inputs
The PI7ALVCHR16269isusedinapplicationsinwhichtwoseparate
portsmustbemultiplexedonto,ordemultiplexedfrom,asingleport.It
isparticularlysuitableasaninterfacebetweensynchronousDRAMs
and high-speed microprocessors.
· Typical V
(Output Ground Bounce)
OLP
< 0.8V atV = 3.3V, T = 25°C
CC
A
· Typical V
(Output V Undershoot)
OH
OHV
< 2.0V atV = 3.3V, T = 25°C
CC
A
Data is stored on the internal B-port registers on the low-to-high
transitionoftheclock(CLK)inputwhentheappropriateclock-enable
(CLKENA) inputs are low. Proper control of these inputs allows two
sequential12-bitwordstobepresentedasa24-bitwordontheB-port.
For data transfer in the B-to-A direction, a single storage register is
provided.Theselect(SEL)lineselects1Bor2BdatafortheAoutputs.
The register on the A output permits the fastest possible data transfer,
thusextendingtheperiodduringwhichthedataisvalidonthebus.The
controlterminalsareregisteredsothatalltransactionsaresynchronous
with CLK. Data flow is controlled by the active-low output enables
(OEA,OEB1,andOEB2).
· All output ports have equivalent 26W series resistors,
no external resistors are required
· Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
· Industrial operation at 40°C to +85°C
· Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Toensurethehigh-impedancestateduringpoweruporpowerdown,
a clock pulse should be applied as soon as possible and OE should
LogicBlockDiagram
be tied to V through a pullup resistor; the minimum value of the
CC
resistorisdeterminedbythecurrent-sinkingcapabilityofthedriver.
Due to OE being routed through a register, the active state of the
outputs cannot be determined prior to the arrival of the first clock
pulse.
Activebus-holdcircuitryisprovidedtoholdunusedorfloatingdata
inputs at a valid logic level.
All outputs are designed to sink up to 12mA and include 26-ohm
resistors to reduce overshoot and undershoot.
PS8372
12/17/99
1