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PI74ALVCHR162245VEX

更新时间： 2024-10-27 13:12:19
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
4页 249K
描述
Bus Transceiver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, 0.635 MM PITCH, PLASTIC, SSOP-48

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PI74ALVCHR162245VEX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP48,.4
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.55其他特性：WITH DIRECTION CONTROL
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
长度：15.875 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.012 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：4.2 ns
传播延迟（tpd）：4.9 ns认证状态：Not Qualified
座面最大高度：2.794 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.5 mm
Base Number Matches：1

PI74ALVCHR162245VEX 数据手册

 浏览型号PI74ALVCHR162245VEX的Datasheet PDF文件第2页浏览型号PI74ALVCHR162245VEX的Datasheet PDF文件第3页浏览型号PI74ALVCHR162245VEX的Datasheet PDF文件第4页 
PI74ALVCHR162245  
3.3V 16-Bit Bidirectional Transceiver  
with 3-State Output  
Product Description  
Product Features  
Pericom Semiconductor’s PI74ALVCH series of logic circuits are  
produced using the Company’s advanced 0.5 micron CMOS  
technology to achieve industry-leading speed grades.  
• PI74ALVCHR162245isdesignedforlowvoltageoperation  
• Vcc=2.3Vto3.6V  
• Hysteresis on all inputs  
The PI74ALVCHR162245 is a 16-bit bidirectional transceiver  
designed for asynchronous two-way communication between data  
buses. The direction control input pin (xDIR) determines the  
direction of data flow through the bidirectional transceiver. The  
Direction and Output Enable controls are designed to operate this  
device as either two independent 8-bit transceivers or one 16-bit  
transceiver. The output enable (OE) input, when HIGH, disables  
both A and B ports by placing them in HIGH Z condition.  
• Typical VOLP (Output Ground Bounce)  
< 0.8V at V = 3.3V, TA = 25°C  
CC  
• Typical VOHV (Output VOH Undershoot)  
< 2.0V at V = 3.3V, TA = 25°C  
CC  
• All output ports have equivilent 26Ω series resistors:  
No external resistors are required  
• Bus Hold retains last active bus state during 3-state  
eliminating the need for external pull-up resistors  
To ensure the high-impedance state during power up or power  
down, OE should be tied to Vcc through a pull-up resistor; the  
minimum value of the resistor is determined by the current sinking  
ability of the driver.  
• Industrial operation at -40°C to +85°C  
• Packages available:  
–48-pin240-milwideplasticTSSOP(A)  
–48-pin300-milwideplasticSSOP(V)  
Active bus-hold circuitry is provided to hold unused or floating  
data inputs at a valid logic level.  
Logic Block Diagram  
1DIR  
2DIR  
1OE  
2OE  
1
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
2
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
1B  
1B  
1B  
1B  
1B  
1B  
1B  
1
B
0
1
2
3
4
5
6
7
2B  
2B  
2B  
2B  
2B  
2B  
2B  
2
B
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
2
2
2
2
2
2
2
PS8343  
10/09/98  
1
1234

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