PI74ALVCH32373
32-Bit Transparent D-Type Latch
with 3-State Outputs
Product Features
ProductDescription
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
• PI74ALVCH32373 is designed for low voltage operation
• V = 2.3V to 3.6V
CC
• Typical V
(Output Ground Bounce)
OLP
This32-bittransparentD-typelatchisdesignedfor2.3Vto3.6VV
operation.
CC
< 0.8V at V = 3.3V, T = 25°C
CC
A
• Typical V
(Output V Undershoot)
OH
OHV
The PI74ALVCH32373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as four 8-bit latches or two 16-
bit latches or one 32-Bit latch. When the Latch Enable (LE) input
is HIGH, the Q outputs follow the (D) inputs. When LE is taken
LOW, the Q outputs are latched at the levels set up at the D inputs.
> 2.0V at V = 3.3V, T = 25°C
CC
A
• Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine
pitch ball grid array, LFBGA (NB)
A buffered Output Enable (OE) input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state in which the outputs neither
loadnordrivethebuslinessignificantly.Thehigh-impedancestate
and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
Product Pin Description
Pin Name
OE
Description
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Data Inputs
LE
Dx
Qx
3-State Outputs
Ground
To ensure the high impedance state during power up or power
GND
down, OE should be tied to V through a pullup resistor; the
CC
minimumvalue of the resistor is determined by the current-sinking
capability of the driver.
V
CC
Power
Truth Table(1)
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Inputs
LE
H
Outputs
OE
D
H
L
Q
H
L
L
L
H
L
H
L
X
X
Q
0
X
Z
Notes:
1. H =HighSignalLevel
L =LowSignalLevel
X =Irrelevant
Z = High Impedance
PS8438
10/14/99
1