Datasheet > PHN203,118

PHN203,118

更新时间： 2024-11-30 19:45:19

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
13页	182K
描述
PHN203 - Dual N-channel TrenchMOS logic level FET SOIC 8-Pin

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技术参数
数据手册

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PHN203,118 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SOIC
针数：	8	Reach Compliance Code：	unknown
风险等级：	5.7	Base Number Matches：	1

PHN203,118 数据手册

PHN203

Dual N-channel TrenchMOS logic level FET

Rev. 05 — 27 April 2010

Product data sheet

1. Product profile

1.1 General description

Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industrial applications only.

1.2 Features and benefits

Suitable for high frequency

applications due to fast switching

characteristics

Suitable for logic level gate drive

sources

1.3 Applications

DC-to-DC converters

Lithium-ion battery applications

1.4 Quick reference data

Table 1.

Symbol

V_DS

Quick reference data

Parameter

Conditions

Min Typ Max Unit

drain-source

voltage

T_j≥ 25 °C; T_j≤ 150 °C

6.3

[1]

I_D

drain current

T_amb= 25 °C; pulsed;

see Figure 1; see Figure 3

P_tot

total power

dissipation

T_amb= 25 °C; pulsed;

see Figure 2

Static characteristics

R_DSondrain-source

V_GS= 10 V; I_D= 7 A; T_j= 25 °C;

see Figure 9; see Figure 10

mΩ

on-state

resistance

Dynamic characteristics

Q_GD

gate-drain charge V_GS= 10 V; I_D= 7 A; V_DS= 15 V;

T_j= 25 °C; see Figure 11

[1] Single device conducting.

12 3 4 5 6 7...13

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