NTB125N02R, NTP125N02R
Power MOSFET
125 A, 24 V N−Channel
TO−220, D2PAK
Features
• Planar HD3e Process for Fast Switching Performance
• Body Diode for Low t and Q and Optimized for Synchronous
http://onsemi.com
rr
rr
Operation
125 AMPERES, 24 VOLTS
• Low C to Minimize Driver Loss
iss
RDS(on) = 3.7 mW (Typ)
• Optimized Q and R
for Shoot−through Protection
gd
DS(on)
• Low Gate Charge
• Pb−Free Packages are Available
D
MAXIMUM RATINGS (T = 25°C Unless otherwise specified)
J
G
Parameter
Drain−to−Source Voltage
Symbol Value Unit
V
24
20
V
V
DSS
dc
S
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
V
GS
dc
R
P
1.1
113.6
°C/W
W
q
JC
MARKING
DIAGRAMS
Total Power Dissipation @ T = 25°C
C
D
Drain Current −
Continuous @ T = 25°C, Chip
I
125
120.5
95
A
A
A
A
4
C
D
Continuous @ T = 25°C, Limited by Package
I
I
I
C
D
D
D
Continuous @ T = 25°C, Limited by Wires
A
Single Pulse (t = 10 ms)
250
p
TO−220AB
CASE 221A
STYLE 5
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ T = 25°C
Drain Current − Continuous @ T = 25°C
125N2RG
AYWW
R
P
I
46
2.72
18.6
°C/W
W
A
q
JA
A
D
A
D
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ T = 25°C
Drain Current − Continuous @ T = 25°C
1
R
P
I
63
1.98
15.9
°C/W
W
A
q
JA
2
2
A
D
3
3
A
D
Operating and Storage Temperature Range
T , T
−55 to
150
°C
J
stg
125N2G
AYWW
2
4
D PAK
Single Pulse Drain−to−Source Avalanche
E
AS
120
mJ
CASE 418AA
STYLE 2
Energy − Starting T = 25°C
J
1
(V = 50 V , V = 10 V , I = 15.5 A ,
DD
dc
GS
dc
L
pk
L = 1 mH, R = 25 W)
G
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
T
L
260
°C
125N2x = Device Code
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
x
= R
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
1. When surface mounted to an FR4 board using 1 inch pad size,
2
(Cu Area 1.127 in ).
2. When surface mounted to an FR4 board using minimum recommended pad
2
size, (Cu Area 0.412 in ).
PIN ASSIGNMENT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
PIN
1
FUNCTION
Gate
2
Drain
3
Source
Drain
4
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 7
NTB125N02R/D