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NBSG16MMNR2 PDF预览

NBSG16MMNR2

更新时间： 2024-11-06 22:27:55
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器转换器时钟
页数 文件大小 规格书
12页 84K
描述
2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

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中文翻译

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NBSG16MMNR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：HVQCCN, LCC16,.12SQ,20
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.49差分输出：YES
驱动器位数：1高电平输入电流最大值：0.0001 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PQCC-N16
JESD-609代码：e0长度：3 mm
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC16,.12SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：240
电源：+-2.5/+-3.3 V认证状态：Not Qualified
最大接收延迟：0.155 ns接收器位数：1
座面最大高度：1 mm子类别：Line Driver or Receivers
最大供电电压：3.465 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn90Pb10)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
最大传输延迟：0.155 ns宽度：3 mm
Base Number Matches：1

NBSG16MMNR2 数据手册

 浏览型号NBSG16MMNR2的Datasheet PDF文件第2页浏览型号NBSG16MMNR2的Datasheet PDF文件第3页浏览型号NBSG16MMNR2的Datasheet PDF文件第4页浏览型号NBSG16MMNR2的Datasheet PDF文件第5页浏览型号NBSG16MMNR2的Datasheet PDF文件第6页浏览型号NBSG16MMNR2的Datasheet PDF文件第7页 
NBSG16M  
2.5V/3.3VꢀMultilevel Input  
to CML Clock/Data  
Receiver/Driver/Translator  
Buffer  
http://onsemi.com  
MARKING  
The NBSG16M is a differential current mode logic (CML)  
receiver/driver/translator buffer. The device is functionally equivalent  
to the EP16, LVEP16, or SG16 devices with CML output structure and  
lower EMI capabilities.  
DIAGRAM*  
Inputs incorporate internal 50 W termination resistors and accept  
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,  
LVCMOS, CML, or LVDS. The CML output structure contains  
SG  
16M  
ALYW  
QFN−16  
MN SUFFIX  
CASE 485G  
internal 50 W source termination resistor to V . The device  
CC  
A
L
Y
W
= Assembly Location  
generates 400 mV output amplitude with 50 W receiver resistor to  
= Wafer Lot  
= Year  
= Work Week  
V
.
CC  
The V pin is internally generated voltage supply available to this  
BB  
device only. For all single−ended input conditions, the unused  
complementary differential input is connected to V as a switching  
BB  
*For additional marking information, refer to  
Application Note AND8002/D.  
reference voltage. V may also rebias AC coupled inputs. When  
BB  
used, decouple V via a 0.01 mF capacitor and limit current sourcing  
BB  
or sinking to 0.5 mA. When not used, V output should be left open.  
BB  
ORDERING INFORMATION  
• Maximum Input Clock Frequency > 10 GHz Typical  
†
Device  
Package  
Shipping  
• Maximum Input Data Rate > 10 Gb/s Typical  
• 120 ps Typical Propagation Delay  
NBSG16MMN  
3x3 mm  
QFN−16  
123 Units / Rail  
• 35 ps Typical Rise and Fall Times  
NBSG16MMNR2  
3x3 mm  
QFN−16  
3000/Tape & Reel  
• Positive CML Output with Operating Range: V = 2.375 V to  
CC  
3.465 V with V = 0 V  
EE  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
• Negative CML Output with RSNECL or NECL Inputs with  
Operating Range: V = 0 V with V = −2.375 V to −3.465 V  
CC  
EE  
• CML Output Level; 400 mV Peak−to−Peak Output with  
50 W Receiver Resistor to V  
CC  
• 50 W Internal Input and Output Termination Resistors  
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL  
and SG Devices  
• V Reference Voltage Output  
BB  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
April, 2004 − Rev. 3  
NBSG16M/D  
1234567...12

中文翻译

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NBSG16MMNR2 替代型号

型号 品牌 替代类型 描述 数据表
NBSG16MMN ONSEMI

类似代替

 2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer
NBSG16MNG ONSEMI

功能相似

 2.5V/3.3V SiGe Differential Receiver/Driver with RSECL Outputs
NBSG16MMNG ONSEMI

功能相似

 2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

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