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NBSG16VSBAR2G

更新时间： 2024-11-19 13:11:59
品牌 Logo 应用领域
安森美 - ONSEMI 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
14页 193K
描述
LINE TRANSCEIVER, PBGA16, 4 X 4 MM, PLASTIC, FCBGA-16

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NBSG16VSBAR2G 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：4 X 4 MM, PLASTIC, FCBGA-16
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.32其他特性：NECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.465V
差分输出：YES驱动器位数：1
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PBGA-B16
长度：4 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified最大接收延迟：0.145 ns
接收器位数：1座面最大高度：1.4 mm
最大供电电压：3.465 V最小供电电压：2.375 V
标称供电电压：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED最大传输延迟：0.145 ns
宽度：4 mmBase Number Matches：1

NBSG16VSBAR2G 数据手册

 浏览型号NBSG16VSBAR2G的Datasheet PDF文件第2页浏览型号NBSG16VSBAR2G的Datasheet PDF文件第3页浏览型号NBSG16VSBAR2G的Datasheet PDF文件第4页浏览型号NBSG16VSBAR2G的Datasheet PDF文件第5页浏览型号NBSG16VSBAR2G的Datasheet PDF文件第6页浏览型号NBSG16VSBAR2G的Datasheet PDF文件第7页 
NBSG16VS  
2.5V/3.3VꢀSiGe Differential  
Receiver/Driver with  
Variable Output Swing  
Description  
http://onsemi.com  
MARKING DIAGRAMS*  
The NBSG16VS is a differential receiver/driver targeted for high  
frequency applications that require variable output swing. The device  
is functionally equivalent to the EP16VS device with much higher  
bandwidth and lower EMI capabilities. This device may be used for  
applications driving VCSEL lasers.  
Inputs incorporate internal 50 ꢀ termination resistors and accept  
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,  
CML, or LVDS. The output amplitude is varied by applying a voltage  
SG  
11  
ALYW  
FCBGA−16  
BA SUFFIX  
CASE 489  
to the V  
input pin. Outputs are variable swing ECL from 100 mV  
CTRL  
to 750 mV amplitude, optimized for operation from V − V  
=
CC  
EE  
3.0 V to 3.465 V.  
16  
The V and V  
pins are internally generated voltage supplies  
1
BB  
MM  
available to this device only. The V is used as a reference voltage  
BB  
SG  
16VS  
ALYWG  
G
for single−ended NECL or PECL inputs and the V  
pin is used as a  
MM  
QFN−16  
MN SUFFIX  
CASE 485G  
reference voltage for LVCMOS inputs. For single−ended input  
operation, the unused complementary differential input is connected to  
V
BB  
or V  
as a switching reference voltage. V or V  
may also  
MM  
BB  
MM  
rebias AC coupled inputs. When used, decouple V and V  
via a  
BB  
MM  
0.01 ꢁ F capacitor and limit current sourcing or sinking to 0.5 mA.  
A
L
= Assembly Location  
= Wafer Lot  
When not used, V and V  
outputs should be left open.  
BB  
MM  
Y
W
G
= Year  
= Work Week  
= Pb−Free Package  
Features  
• Maximum Input Clock Frequency up to 12 GHz Typical  
• Maximum Input Data Rate up to 12 Gb/s Typical  
(Note: Microdot may be in either location)  
• 40 ps Typical Rise and Fall Times (V  
• 120 ps Typical Propagation Delay (V  
= V − 1 V)  
CTRL  
CC  
= V − 1 V)  
CTRL  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
• Variable Swing PECL Output with Operating Range: V = 2.375 V to  
CC  
3.465 V with V = 0 V  
EE  
• Variable Swing NECL Output with NECL Inputs with  
Operating Range: V = 0 V with V = −2.375 V to −3.465 V  
ORDERING INFORMATION  
CC  
EE  
See detailed ordering and shipping information in the package  
dimensions section on page 12 of this data sheet.  
• Output Level (100 mV to 750 mV Peak−to−Peak Output;  
− V = 3.0 V to 3.465 V), Differential Output Only  
V
CC  
EE  
• 50 ꢀ Internal Input Termination Resistors  
• Compatible with Existing 2.5 V/3.3 V EP Devices  
• V and V  
Reference Voltage Output  
BB  
MM  
• Pb−Free Packages are Available  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
July, 2006 − Rev. 7  
NBSG16VS/D  
1234567...14

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