NBSG53A

更新时间： 2024-11-18 22:27:55

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
18页	135K
描述
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS

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NBSG53A 数据手册

NBSG53A

2.5V/3.3VꢀSiGe Selectable

Differential Clock and Data

D Flip−Flop/Clock Divider

with Reset and OLS*

http://onsemi.com

MARKING

The NBSG53A is a multi−function differential D flip−flop (DFF) or

fixed divide by two (DIV/2) clock generator. This is a part of the

GigaComm

family of high performance Silicon Germanium

DIAGRAM**

products. A strappable control pin is provided to select between the

two functions. The device is housed in a low profile 4x4 mm 16−pin

Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.

The NBSG53A is a device with data, clock, OLS, reset, and select

inputs. Differential inputs incorporate internal 50 W termination

resistors and accept NECL (Negative ECL), PECL (Positive ECL),

LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to

program the peak−to−peak output amplitude between 0 and 800 mV

in five discrete steps. The RESET and SELECT inputs are

single−ended and can be driven with either LVECL or

LVCMOS/LVTTL input levels.

53A

LYW

FCBGA−16

BA SUFFIX

CASE 489

SG53A

ALYW

Data is transferred to the outputs on the positive edge of the clock.

The differential clock inputs of the NBSG53A allow the device to also

be used as a negative edge triggered device.

QFN−16

MN SUFFIX

CASE 485G

A = Assembly Location

L = Wafer Lot

• Maximum Input Clock Frequency (DFF) > 8 GHz Typical

(See Figures 4, 6, 8, 10, and 11)

Y = Year

W = Work Week

• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical

(See Figures 5, 7, 9, 10, and 11)

**For further details, refer to Application

Note AND8002/D

• 210 ps Typical Propagation Delay (OLS = FLOAT)

• 45 ps Typical Rise and Fall Times (OLS = FLOAT)

• DIV/2 Mode (Active with Select Low)

• DFF Mode (Active with Select High)

Board

Description

NBSG53ABAEVB NBSG53ABA Evaluation Board

• Selectable Swing PECL Output with Operating Range: V = 2.375 V

to 3.465 V with V = 0 V

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 16 of this data sheet.

• Selectable Swing NECL Output with NECL Inputs with

Operating Range: V = 0 V with V = −2.375 V to −3.465 V

• Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV

Peak−to−Peak Output)

• 50 W Internal Input Termination Resistors on all Differential Inputs

*Output Level Select

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

March, 2004 − Rev. 5

NBSG53A/D

12 3 4 5 6 7...18

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与NBSG53A相关器件

型号	品牌	获取价格	描述	数据表
NBSG53A/D	ETC	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53A_06	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with
NBSG53A_14	ONSEMI	获取价格	2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider
NBSG53ABA	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53ABAEVB	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53ABAG	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM
NBSG53ABAHTBG	ONSEMI	获取价格	IC 53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4
NBSG53ABAR2	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53ABAR2G	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM
NBSG53AMA1TBG	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM

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