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NBSG53MN PDF预览

NBSG53MN

更新时间: 2024-11-19 17:58:23
品牌 Logo 应用领域
安森美 - ONSEMI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
16页 121K
描述
LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16, 3 X 3 MM, QFN-16

NBSG53MN 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:3 X 3 MM, QFN-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.76其他特性:NECL OPERATING RANGE: VCC = 0 V WITH VEE = -2.375 V TO -3.465 V
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N16
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:16
实输出次数:1最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC16,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):240电源:-2.5/-3.3/2.5/3.3 V
Prop。Delay @ Nom-Sup:0.275 ns传播延迟(tpd):0.285 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

NBSG53MN 数据手册

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NBSG53A  
2.5V/3.3VꢀSiGe Selectable  
Differential Clock and Data  
D Flip−Flop/Clock Divider  
with Reset and OLS*  
http://onsemi.com  
MARKING  
The NBSG53A is a multi-function differential D flip-flop (DFF) or  
fixed divide by two (DIV/2) clock generator. This is a part of the  
GigaComm  
family of high performance Silicon Germanium  
DIAGRAM**  
products. A strappable control pin is provided to select between the  
two functions. The device is housed in a low profile 4x4 mm 16-pin  
Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.  
The NBSG53A is a device with data, clock, OLS, reset, and select  
inputs. Differential inputs incorporate internal 50 W termination  
resistors and accept NECL (Negative ECL), PECL (Positive ECL),  
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to  
program the peak- to- peak output amplitude between 0 and 800 mV  
in five discrete steps. The RESET and SELECT inputs are  
single- ended and can be driven with either LVECL or  
LVCMOS/LVTTL input levels.  
SG  
53A  
LYW  
FCBGA-16  
BA SUFFIX  
CASE 489  
SG53A  
ALYW  
Data is transferred to the outputs on the positive edge of the clock.  
The differential clock inputs of the NBSG53A allow the device to also  
be used as a negative edge triggered device.  
QFN-16  
MN SUFFIX  
CASE 485G  
A = Assembly Location  
L = Wafer Lot  
Maximum Input Clock Frequency (DFF) > 8 GHz Typical  
(See Figures 4, 6, 8, 10, and 11)  
Y = Year  
W = Work Week  
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical  
(See Figures 5, 7, 9, 10, and 11)  
**For further details, refer to Application  
Note AND8002/D  
210 ps Typical Propagation Delay (OLS = FLOAT)  
45 ps Typical Rise and Fall Times (OLS = FLOAT)  
DIV/2 Mode (Active with Select Low)  
DFF Mode (Active with Select High)  
ORDERING INFORMATION  
Device  
Package  
Shipping  
NBSG53ABA  
4x4 mm  
FCBGA-16  
100 Units/Tray  
Selectable Swing PECL Output with Operating Range: V = 2.375 V  
CC  
to 3.465 V with V = 0 V  
EE  
NBSG53ABAR2  
4x4 mm  
FCBGA-16  
500/Tape & Reel  
Selectable Swing NECL Output with NECL Inputs with  
Operating Range: V = 0 V with V = -2.375 V to -3.465 V  
CC  
EE  
NBSG53MN  
3x3 mm  
QFN-16  
123 Units/Rail  
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV  
Peak-to-Peak Output)  
NBSG53MNR2  
3x3 mm  
QFN-16  
3000/Tape & Reel  
50 W Internal Input Termination Resistors on all Differential Inputs  
*Output Level Select  
Board  
Description  
NBSG53ABAEVB NBSG53ABA Evaluation Board  
Semiconductor Components Industries, LLC, 2003  
46  
Publication Order Number:  
April, 2003 - Rev. 4  
NBSG53A/D  

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