Datasheet > NBSG53A_14

NBSG53A_14

更新时间： 2024-11-20 01:21:51

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
17页	167K
描述
2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider

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NBSG53A_14 数据手册

NBSG53A

2.5 V/3.3 VꢀSiGe Selectable

Differential Clock and Data

D Flip-Flop/Clock Divider

with Reset and OLS*

http://onsemi.com

The NBSG53A is a multi-function differential D flip-flop (DFF) or

fixed divide by two (DIV/2) clock generator. This is a part of the

GigaCommt family of high performance Silicon Germanium

products. A strappable control pin is provided to select between the

two functions. The device is housed in a low profile 4x4 mm 16-pin

Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.

The NBSG53A is a device with data, clock, OLS*, reset, and select

inputs. Differential inputs incorporate internal 50 W termination

resistors and accept NECL (Negative ECL), PECL (Positive ECL),

LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to

program the peak-to-peak output amplitude between 0 and 800 mV

in five discrete steps. The RESET and SELECT inputs are

single-ended and can be driven with either LVECL or

LVCMOS/LVTTL input levels.

QFN−16

MN SUFFIX

CASE 485G

MARKING DIAGRAM*

53A

ALYWG

Data is transferred to the outputs on the positive edge of the clock.

The differential clock inputs of the NBSG53A allow the device to also

be used as a negative edge triggered device.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Maximum Input Clock Frequency (DFF) > 8 GHz Typical

(See Figures 3, 5, 7, 9, and 10)

• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical

(See Figures 4, 6, 8, 9, and 10)

(Note: Microdot may be in either location)

• 210 ps Typical Propagation Delay (OLS = FLOAT)

*For additional marking information, refer to

Application Note AND8002/D.

• 45 ps Typical Rise and Fall Times (OLS = FLOAT)

• DIV/2 Mode (Active with Select Low)

• DFF Mode (Active with Select High)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

• Selectable Swing PECL Output with Operating Range: V = 2.375 V

dimensions section on page 16 of this data sheet.

to 3.465 V with V = 0 V

• Selectable Swing NECL Output with NECL Inputs with

Operating Range: V = 0 V with V = −2.375 V to −3.465 V

• Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV

Peak-to-Peak Output)

• 50 W Internal Input Termination Resistors on all Differential Inputs

• These are Pb-Free Devices

*Output Level Select

Publication Order Number:

June, 2014 − Rev. 15

NBSG53A/D

12 3 4 5 6 7...17

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与NBSG53A_14相关器件

型号	品牌	获取价格	描述	数据表
NBSG53ABA	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53ABAEVB	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53ABAG	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM
NBSG53ABAHTBG	ONSEMI	获取价格	IC 53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4
NBSG53ABAR2	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset
NBSG53ABAR2G	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM
NBSG53AMA1TBG	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM
NBSG53AMAG	ONSEMI	获取价格	暂无描述
NBSG53AMAHTBG	ONSEMI	获取价格	53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA16, 4 X 4 MM
NBSG53AMN	ONSEMI	获取价格	2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset

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