NB6L11S
2.5 V 1:2 AnyLevelt Input
to LVDS Fanout Buffer /
Translator
The NB6L11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevelt input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to LVDS and two
identical copies of Clock or Data will be distributed, operating up to
2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6L11S is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock or Data
distribution applications.
http://onsemi.com
MARKING
DIAGRAM*
16
1
The NB6L11S has a wide input common mode range from
NB6L
11S
1
GND + 50 mV to V − 50 mV. Combined with the 50 W internal
CC
termination resistors at the inputs, the NB6L11S is ideal for translating
a variety of differential or single−ended Clock or Data signals to
350 mV typical LVDS output levels.
ALYW G
QFN−16
MN SUFFIX
CASE 485G
G
The NB6L11S is the 2.5 V version of the NB6N11S and is offered in
a small 3 mm X 3 mm 16−QFN package. Application notes, models,
and support documentation are available at www.onsemi.com.
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 380 ps Typical Propagation Delay
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
• 120 ps Typical Rise and Fall Times
V
V
• Single Power Supply; V = 2.5 V " 5%
Q0
TD
CC
• These are Pb−Free Devices
D
D
TD
Q1
Q1
Figure 1. Logic Diagram
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
September, 2006 − Rev. 2
NB6L11S/D