NB6L16DT

更新时间： 2024-12-01 03:46:59

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器转换器时钟
页数	文件大小	规格书
12页	188K
描述
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer

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中文翻译

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替代型号

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NB6L16DT 数据手册

NB6L16

2.5V / 3.3V Multilevel Input to

Differential LVPECL/LVNECL

Clock or Data Receiver/

Driver/Translator Buffer

http://onsemi.com

MARKING

The NB6L16 is a high precision, low power ECL differential clock

or data receiver/driver/translator buffer. The device is functionally

equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With

output transition times of 70 ps, it is ideally suited for high frequency,

low power systems. The device is targeted for Backplane buffering,

GbE clock/data distribution, Fibre Channel distribution and SONET

clock/data distribution applications.

Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),

LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV

ECL signals.

DIAGRAMS*

6L16

ALYW

SOIC−8

D SUFFIX

CASE 751

The V pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

6L16

may also rebias AC coupled inputs. When used, decouple V

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

Features

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Maximum Input Clock Frequency w 6 GHz Typical

• Maximum Input Data Rate Frequency w 6 Gb/s Typical

• Low 12 mA Typical Power Supply Current

• 70 ps Typical Rise/Fall Times

(Note: Microdot may be in either location)

• 130 ps Input Propagation Delay

*For additional marking information, refer to

Application Note AND8002/D.

• On−Chip Reference for ECL Single−Ended Input − V Output

• PECL Mode Operating Range:

= 2.375 V to 3.465 V with V = 0 V

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

• NECL Mode Operating Range:

= 0 V with V = −2.375 V to −3.465 V

• Open Input Default State

• LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input

Compatible

• Pb−Free Packages are Available

Semiconductor Components Industries, LLC, 2007

Publication Order Number:

March, 2007 − Rev. 6

NB6L16/D

12 3 4 5 6 7...12

中文翻译

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NB6L16DT 替代型号

型号	品牌	替代类型	描述	数据表
NB6L16DTR2	ONSEMI	完全替代	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/

与NB6L16DT相关器件

型号	品牌	获取价格	描述	数据表
NB6L16DTG	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16DTR2	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16DTR2G	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L239	ONSEMI	获取价格	2.5 V / 3.3 V Any Differential Clock IN to Di
NB6L239_06	ONSEMI	获取价格	2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock
NB6L239MN	ONSEMI	获取价格	2.5 V / 3.3 V Any Differential Clock IN to Di
NB6L239MNG	ONSEMI	获取价格	2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock
NB6L239MNR2	ONSEMI	获取价格	2.5 V / 3.3 V Any Differential Clock IN to Di
NB6L239MNR2G	ONSEMI	获取价格	2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock
NB6L295	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs

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