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NB6L239 PDF预览

NB6L239

更新时间: 2024-11-05 22:27:11
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
12页 93K
描述
2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ±1/2/4/8, ±2/4/8/16 Clock Divider

NB6L239 数据手册

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NB6L239  
2.5 V / 3.3 V Any Differential  
Clock IN to Differential  
LVPECL OUT ÷1/2/4/8,  
÷2/4/8/16 Clock Divider  
Features  
http://onsemi.com  
The NB6L239 is a high−speed, low skew clock divider with two  
divider circuits, each having selectable clock divide ratios; B1/2/4/8  
and B2/4/8/16. Both divider circuits drive a pair of differential  
LVPECL outputs. (More device information on page 7).  
MARKING DIAGRAM*  
Maximum Clock Input Frequency, 3.0 GHz  
Input Compatibility with LVDS/LVPECL/CML/HSTL  
Rise/Fall Time 70 ps Typical  
XXXX  
XXXX  
ALYW  
Bottom View  
QFN−16  
MN SUFFIX  
CASE 485G  
< 10 ps Typical Output−to−Output Skew  
Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs  
Internal 50 W Termination Provided  
Random Clock Jitter < 1 ps RMS  
XXXX = Device Code  
A
L
= Assembly Location  
= Wafer Lot  
Y
W
= Year  
= Work Week  
Divide−by−1 Edge of QA Aligned to QB Divided Output  
Operating Range: V = 2.375 V to 3.465 V with V = 0 V  
CC  
EE  
*For additional marking information, refer to  
Application Note AND8002/D.  
Master Reset for Synchronization of Multiple Chips  
V  
Reference Output  
BBAC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
Synchronous Output Enable/Disable  
dimensions section on page 11 of this data sheet.  
SELA0  
SELA1  
QA  
QA  
CLK  
VT  
CLK  
QB  
QB  
EN  
SELB0  
SELB1  
+
MR  
Figure 1. Simplified Logic Diagram  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
April, 2004 − Rev. 0  
NB6L239/D  

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