Datasheet > NB6L56MNG

NB6L56MNG

更新时间： 2024-09-17 01:12:31

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
10页	139K
描述
Dual 2:1 Differential Clock Data Multiplexer

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中文翻译

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NB6L56MNG 数据手册

NB6L56

2.5V / 3.3V Dual 2:1

Differential Clock / Data

Multiplexer with LVPECL

Outputs

http://onsemi.com

Multi−Level Inputs w/ Internal Termination

QFN32

MN SUFFIX

CASE 488AM

The NB6L56 is a high performance Dual 2−to−1 Differential Clock

or Data multiplexer. The differential inputs incorporate internal 50 W

termination resistors that are accessed through the VT pin. This feature

allows the NB6L56 to accept various Differential logic level

standards, such as LVPECL, CML or LVDS. Outputs are 800 mV

LVPECL signals. For interface options see Figures 12 − 15.

The NB6L56 produces minimal Clock or Data jitter operating up to

2.5 GHz or 2.5 Gbps, respectively. As such, the NB6L56 is ideal for

SONET, GigE, Fiber Channel, Backplane and other Clock/Data

distribution applications.

MARKING DIAGRAM*

NB6L

AWLYYWWG

The NB6L56 is offered in a low profile 5 mm x 5 mm 32−pin QFN

package and is a member of the ECLinPS MAX™ family of high

performance Clock / Data products. Application notes, models, and

support documentation are available at www.onsemi.com.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Maximum Input Data Rate > 2.5 Gbps

• Maximum Input Clock Frequency > 2.5 GHz

*For additional marking information, refer to

Application Note AND8002/D.

• Jitter

< 1 ps RMS RJ (Data)

< 10 ps PP DJ (Data)

< 0.7 ps RMS Crosstalk induced jitter (CLOCK)

• 360 ps Max Propagation Delay

• 180 ps Max Rise and Fall Times

• Operating Range:

= 2.5 5% (2.375 V to 2.625 V)

=3.3 10% (3.0 V to 3.6 V)

• Internal 50 W Input Termination Resistors

• Industrial Temp. Range (−40°C to 85°C)

• QFN−32 Package

• These are Pb−Free Devices

Applications

• Clock and Data Distribution

• Networking and Communications

• High End Computing

• Wireless and Wired Infrastructure

End Products

Figure 1. Simplified Logic Diagram

ORDERING INFORMATION

• Servers

• Ethernet Switch/Routers

• ATE

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

• Test and Measurement

Publication Order Number:

May, 2012 − Rev. 0

NB6L56/D

12 3 4 5 6 7...10

中文翻译

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NB6L56MNG 替代型号

型号	品牌	替代类型	描述	数据表
NB6L56MNTXG	ONSEMI	类似代替	Dual 2:1 Differential Clock Data Multiplexer

与NB6L56MNG相关器件

型号	品牌	获取价格	描述	数据表
NB6L56MNTXG	ONSEMI	获取价格	Dual 2:1 Differential Clock Data Multiplexer
NB6L572M	ONSEMI	获取价格	2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator
NB6L572MMNG	ONSEMI	获取价格	2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator
NB6L572MMNR4G	ONSEMI	获取价格	2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator
NB6L611	ONSEMI	获取价格	2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer
NB6L611MNG	ONSEMI	获取价格	2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer
NB6L611MNR2G	ONSEMI	获取价格	2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer
NB6L72	ONSEMI	获取价格	2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with LVPECL Outputs
NB6L72M	ONSEMI	获取价格	2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with CML Outputs
NB6L72M_07	ONSEMI	获取价格	2.5V / 3.3V Differential 2 X 2 Crosspoint Switch with CML Outputs

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