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NB6N14SMNG PDF预览

NB6N14SMNG

更新时间: 2024-01-05 22:42:21
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 177K
描述
3.3 V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator

NB6N14SMNG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC16,.12SQ,20
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:1.1
系列:6N输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N16长度:3 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC16,.12SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:0.6 ns
传播延迟(tpd):0.6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.02 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Gold/Palladium (Ni/Au/Pd)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:3 mm
Base Number Matches:1

NB6N14SMNG 数据手册

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NB6N14S  
3.3 V 1:4 AnyLevelt  
Differential Input to LVDS  
Fanout Buffer/Translator  
The NB6N14S is a differential 1:4 Clock or Data Receiver and will  
accept AnyLevelt differential input signals: LVPECL, CML or  
LVDS. These signals will be translated to LVDS and four identical  
copies of Clock or Data will be distributed, operating up to 2.0 GHz or  
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,  
GigE, Fiber Channel, Backplane and other Clock or Data distribution  
applications.  
http://onsemi.com  
MARKING  
DIAGRAM*  
16  
1
The NB6N14S has a wide input common mode range from  
NB6N  
14S  
1
GND + 50 mV to V 50 mV. Combined with the 50 W internal  
CC  
termination resistors at the inputs, the NB6N14S is ideal for  
translating a variety of differential or singleended Clock or Data  
signals to 350 mV typical LVDS output levels.  
QFN16  
ALYW G  
MN SUFFIX  
CASE 485G  
G
The NB6N14S is offered in a small 3 mm x 3 mm 16QFN  
package. Application notes, models, and support documentation are  
available at www.onsemi.com.  
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
The NB6N14S is a member of the ECLinPS MAXt family of high  
W = Work Week  
G
performance products.  
= PbFree Package  
Features  
(Note: Microdot may be in either location)  
Maximum Input Clock Frequency > 2.0 GHz  
Maximum Input Data Rate > 2.5 Gb/s  
1 ps Maximum RMS Clock Jitter  
Typically 10 ps Data Dependent Jitter  
380 ps Typical Propagation Delay  
120 ps Typical Rise and Fall Times  
*For additional marking information, refer to  
Application Note AND8002/D.  
Q0  
Q0  
V  
Reference Output  
REF_AC  
TIA/EIA 644 Compliant  
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and  
SG Devices  
These are PbFree Devices  
Q1  
Q1  
IN  
VT  
/IN  
W
50  
W
50  
Q2  
Q2  
EN  
(LVTTL/CMOS)  
D
Q
Q3  
Q3  
V
REF_AC  
Device DDJ = 10 ps  
Figure 1. Logic Diagram  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
TIME (58 ps/div)  
Figure 2. Typical Output Waveform at 2.488 Gb/s with  
PRBS 2231 (VINPP = 400 mV; Input Signal DDJ = 14 ps)  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
January, 2007 Rev. 3  
NB6N14S/D  

NB6N14SMNG 替代型号

型号 品牌 替代类型 描述 数据表
SY89833ALMG MICREL

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