NB6L295

更新时间： 2024-11-06 11:56:55

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
14页	196K
描述
2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs

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NB6L295 数据手册

NB6L295

2.5V / 3.3V Dual Channel

Programmable Clock/Data

Delay with Differential

LVPECL Outputs

Multi−Level Inputs w/ Internal Termination

http://onsemi.com

MARKING

The NB6L295 is a Dual Channel Programmable Delay Chip

designed primarily for Clock or Data de−skewing and timing

adjustment. The NB6L295 is versatile in that two individual variable

delay channels, PD0 and PD1, can be configured in one of two

operating modes, a Dual Delay or an Extended Delay.

In the Dual Delay Mode, each channel has a programmable delay

section which is designed using a matrix of gates and a chain of

multiplexers. There is a fixed minimum delay of 3.2 ns per channel.

The Extended Delay Mode amounts to the additive delay of PD0

plus PD1 and is accomplished with the Serial Data Interface MSEL bit

set High. This will internally cascade the output of PD0 into the input

of PD1. Therefore, the Extended Delay path starts at the IN0/IN0

inputs, flows through PD0, cascades to the PD1 and outputs through

Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended

Delay Mode.

DIAGRAM*

QFN−24

MN SUFFIX

CASE 485L

NB6L

295

ALYWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

The required delay is accomplished by programming each delay

channel via a 3−pin Serial Data Interface, described in the application

section. The digitally selectable delay has an increment resolution of

typically 11 ps with a net programmable delay range of either 0 ns to

6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the

Extended Delay Mode.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

The Multi−Level Inputs can be driven directly by differential

LVPECL, LVDS or CML logic levels; or by single ended LVPECL,

LVCMOS or LVTTL. A single enable pin is available to control both

inputs. The SDI input pins are controlled by LVCMOS or LVTTL

level signals. The NB6L295 LVPECL output contains temperature

compensation circuitry. This device is offered in a 4 mm x 4 mm

24−pin QFN Pb−free package. The NB6L295 is a member of the

ECLinPS MAX™ family of high performance products.

• Input Clock Frequency > 1.5 GHz with 550 mV

• 3 ps Typical Clock Jitter, RMS

OUTPP

• 20 ps Pk−Pk Typical Data Dependent Jitter

• Input Data Rate > 2.5 Gb/s

• LVPECL, CML or LVDS Differential Input Compatible

• LVPECL, LVCMOS, LVTTL Single−Ended Input

Compatible

• Programmable Delay Range: 0 ns to 6 ns per Delay

Channel

• Programmable Delay Range: 0 ns to 11.2 ns for

Extended Delay Mode

• 3−Wire Serial Interface

• Operating Range: V = 2.375 V to 3.6 V

• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel

• LVPECL Output Level; 780 mV Peak−to−Peak, Typical

• Internal 50 W Input Termination Provided

• −40°C to 85°C Ambient Operating Temperature

• 24−Pin QFN, 4 mm x 4 mm

• Total Delay Range: 6 ns to 17 ns in Extended Delay

Mode

• Monotonic Delay: 11 ps Increments in 511 Steps

• Linearity $20 ps, Maximum

• These are Pb−Free Devices*

• 100 ps Typical Rise and Fall Times

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Publication Order Number:

January, 2010 − Rev. 3

NB6L295/D

12 3 4 5 6 7...14

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与NB6L295相关器件

型号	品牌	获取价格	描述	数据表
NB6L295_12	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs
NB6L295M	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
NB6L295M_12	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
NB6L295MMNG	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
NB6L295MMNGEVB	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
NB6L295MMNTXG	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs
NB6L295MNG	ONSEMI	获取价格	Dual Channel Programmable Delay Line with LVPECL Output, QFN24, 4x4, 0.5P, 92-TUBE
NB6L295MNGEVB	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs
NB6L295MNTXG	ONSEMI	获取价格	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs
NB6L56	ONSEMI	获取价格	Dual 2:1 Differential Clock Data Multiplexer

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