Datasheet > NB6L14S

NB6L14S

更新时间： 2024-11-06 05:51:55

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
11页	210K
描述
2.5 V 1:4 AnyLevel™ Differential Input to LVDS Fanout Buffer/Translator

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NB6L14S 数据手册

NB6L14S

2.5 V 1:4 AnyLevel]

Differential Input to LVDS

Fanout Buffer/Translator

The NB6L14S is a differential 1:4 Clock or Data Receiver and will

accept AnyLevel differential input signals: LVPECL, CML, LVDS, or

HSCL. These signals will be translated to LVDS and four identical

copies of Clock or Data will be distributed, operating up to 2.0 GHz or

2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET,

GigE, Fiber Channel, Backplane and other Clock or Data distribution

applications.

http://onsemi.com

MARKING

DIAGRAM*

The NB6L14S has a wide input common mode range from

NB6L

14S

GND + 50 mV to V − 50 mV. Combined with the 50 W internal

QFN−16

MN SUFFIX

CASE 485G

ALYW G

termination resistors at the inputs, the NB6L14S is ideal for translating

a variety of differential or single−ended Clock or Data signals to

350 mV typical LVDS output levels.

The NB6L14S is the 2.5 V version of the NB6N14S and is offered

in a small 3 mm x 3 mm 16−QFN package. Application notes, models,

and support documentation are available at www.onsemi.com.

The NB6L14S is a member of the ECLinPS MAX™ family of high

performance products.

= Assembly Location

= Wafer Lot

= Year

W = Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

Features

*For additional marking information, refer to

Application Note AND8002/D.

• Maximum Input Clock Frequency > 2.0 GHz

• Maximum Input Data Rate > 2.5 Gb/s

• 1 ps Maximum of RMS Clock Jitter

• Typically 10 ps of Data Dependent Jitter

• 380 ps Typical Propagation Delay

• 120 ps Typical Rise and Fall Times

• Single Power Supply; V = 2.5 $ 5%

• V

Reference Output

REF_AC

• These are Pb−Free Devices

(LVTTL/CMOS)

REFAC

Device DDJ = 10 ps

Figure 1. Logic Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

TIME (58 ps/div)

Figure 2. Typical Output Waveform at 2.488 Gb/s with

PRBS 2²³⁻¹(V_INPP= 400 mV; Input Signal DDJ = 14 ps)

Semiconductor Components Industries, LLC, 2009

Publication Order Number:

June, 2009 − Rev. 0

NB6L14S/D

12 3 4 5 6 7...11

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与NB6L14S相关器件

型号	品牌	获取价格	描述	数据表
NB6L14S_11	ONSEMI	获取价格	Differential Input to LVDS Fanout Buffer/Translator
NB6L14SMNG	ONSEMI	获取价格	2.5 V 1:4 AnyLevel™ Differential Input to LVD
NB6L14SMNTWG	ONSEMI	获取价格	Differential Input to LVDS Fanout Buffer/Translator
NB6L14SMNTXG	ONSEMI	获取价格	2.5 V 1:4 AnyLevel™ Differential Input to LVD
NB6L16	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16_07	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16D	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16DG	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16DR2	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16DR2G	ONSEMI	获取价格	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/

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