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NB6L16DR2G PDF预览

NB6L16DR2G

更新时间： 2024-11-06 03:46:59
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器转换器时钟
页数 文件大小 规格书
12页 188K
描述
2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer

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NB6L16DR2G 数据手册

 浏览型号NB6L16DR2G的Datasheet PDF文件第2页浏览型号NB6L16DR2G的Datasheet PDF文件第3页浏览型号NB6L16DR2G的Datasheet PDF文件第4页浏览型号NB6L16DR2G的Datasheet PDF文件第5页浏览型号NB6L16DR2G的Datasheet PDF文件第6页浏览型号NB6L16DR2G的Datasheet PDF文件第7页 
NB6L16  
2.5V / 3.3V Multilevel Input to  
Differential LVPECL/LVNECL  
Clock or Data Receiver/  
Driver/Translator Buffer  
http://onsemi.com  
MARKING  
The NB6L16 is a high precision, low power ECL differential clock  
or data receiver/driver/translator buffer. The device is functionally  
equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With  
output transition times of 70 ps, it is ideally suited for high frequency,  
low power systems. The device is targeted for Backplane buffering,  
GbE clock/data distribution, Fibre Channel distribution and SONET  
clock/data distribution applications.  
Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),  
LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV  
ECL signals.  
DIAGRAMS*  
8
8
6L16  
1
ALYW  
G
SOIC−8  
D SUFFIX  
CASE 751  
1
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single−ended input conditions, the unused  
8
8
differential input is connected to V as a switching reference voltage.  
BB  
1
6L16  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
ALYWG  
TSSOP−8  
DT SUFFIX  
CASE 948R  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
G
to 0.5 mA. When not used, V should be left open.  
BB  
1
Features  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
• Maximum Input Clock Frequency w 6 GHz Typical  
• Maximum Input Data Rate Frequency w 6 Gb/s Typical  
• Low 12 mA Typical Power Supply Current  
• 70 ps Typical Rise/Fall Times  
(Note: Microdot may be in either location)  
• 130 ps Input Propagation Delay  
*For additional marking information, refer to  
Application Note AND8002/D.  
• On−Chip Reference for ECL Single−Ended Input − V Output  
BB  
• PECL Mode Operating Range:  
V
CC  
= 2.375 V to 3.465 V with V = 0 V  
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
• NECL Mode Operating Range:  
= 0 V with V = −2.375 V to −3.465 V  
V
CC  
EE  
• Open Input Default State  
• LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input  
Compatible  
• Pb−Free Packages are Available  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
March, 2007 − Rev. 6  
NB6L16/D  
1234567...12

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NB6L16DR2G 替代型号

型号 品牌 替代类型 描述 数据表
NB6L16DR2 ONSEMI

完全替代

 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16D ONSEMI

完全替代

 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/
NB6L16DG ONSEMI

类似代替

 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/

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NB6L239MNR2G ONSEMI

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