Datasheet > 存储 > SRAM> MCM69F536CTQ8.5R

MCM69F536CTQ8.5R

更新时间： 2024-09-18 22:25:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器信息通信管理
页数	文件大小	规格书
12页	213K
描述
32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

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技术参数
数据手册

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MCM69F536CTQ8.5R 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.52	最长访问时间：	8.5 ns
其他特性：	SELF TIMED WRITE CYCLE; BYTE WRITE CONTROL	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	1179648 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
功能数量：	1	端口数量：	1
端子数量：	100	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	110 °C	最低工作温度：	20 °C
组织：	32KX36	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.055 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.32 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

MCM69F536CTQ8.5R 数据手册

Order this document

by MCM69F536C/D

SEMICONDUCTOR TECHNICAL DATA

MCM69F536C

32K x 36 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F536C is a 1M–bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 32K

words of 36 bits each. This device integrates input registers, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

controlwiththeuseofanexternalclock(K). BiCMOScircuitryreducestheoverall

power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

TQ PACKAGE

TQFP

CASE 983A–01

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F536C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and

synchronous write enable SW are provided to allow writes to either individual

bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa

controls DQa, SBb controls DQb, and so on. Individual bytes are written if the

selected byte writes SBxare asserted with SW. AllbytesarewrittenifeitherSGW

is asserted or if all SBx and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F536C operates from a 3.3 V power supply and all inputs and

outputs are LVTTL compatible.

•

MCM69F536C–8.5 = 8.5 ns Access / 12 ns Cycle

MCM69F536C–9 = 9 ns Access / 12 ns Cycle

MCM69F536C–10 = 10 ns Access / 15 ns Cycle

MCM69F536C–12 = 12 ns Access / 16.6 ns Cycle

Single 3.3 V + 10%, – 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

5 V Tolerant on all Pins (Inputs and I/Os)

100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

REV 3

2/18/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F536C

12 3 4 5 6 7...12

中文翻译

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与MCM69F536CTQ8.5R相关器件

型号	品牌	获取价格	描述	数据表
MCM69F536CTQ9	MOTOROLA	获取价格	32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F536CTQ9R	MOTOROLA	获取价格	32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F536CTQ9R	NXP	获取价格	IC,SYNC SRAM,32KX36,BICMOS-TTL,QFP,100PIN,PLASTIC
MCM69F536TQ10	MOTOROLA	获取价格	Cache SRAM, 32KX36, 10ns, BICMOS, PQFP100, TQFP-100
MCM69F536TQ10R	MOTOROLA	获取价格	32KX36 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F536TQ12	MOTOROLA	获取价格	Cache SRAM, 32KX36, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F536TQ12R	MOTOROLA	获取价格	32KX36 CACHE SRAM, 12ns, PQFP100, TQFP-100
MCM69F536TQ8.5	MOTOROLA	获取价格	32KX36 CACHE SRAM, 8.5ns, PQFP100, TQFP-100
MCM69F536TQ8.5R	MOTOROLA	获取价格	Cache SRAM, 32KX36, 8.5ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ10R	MOTOROLA	获取价格	64KX18 CACHE SRAM, 10ns, PQFP100, TQFP-100

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