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MCM69F618ATQ9 PDF预览

MCM69F618ATQ9

更新时间: 2024-09-19 14:53:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器内存集成电路
页数 文件大小 规格书
12页 351K
描述
Cache SRAM, 64KX18, 9ns, BICMOS, PQFP100, TQFP-100

MCM69F618ATQ9 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP,
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.52Is Samacsys:N
最长访问时间:9 ns其他特性:BURST COUNTER
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:1179648 bit
内存集成电路类型:CACHE SRAM内存宽度:18
功能数量:1端口数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:110 °C最低工作温度:20 °C
组织:64KX18输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

MCM69F618ATQ9 数据手册

 浏览型号MCM69F618ATQ9的Datasheet PDF文件第2页浏览型号MCM69F618ATQ9的Datasheet PDF文件第3页浏览型号MCM69F618ATQ9的Datasheet PDF文件第4页浏览型号MCM69F618ATQ9的Datasheet PDF文件第5页浏览型号MCM69F618ATQ9的Datasheet PDF文件第6页浏览型号MCM69F618ATQ9的Datasheet PDF文件第7页 
Order this document  
by MCM69F618A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69F618A  
64K x 18 Bit Flow–Through  
BurstRAM Synchronous  
Fast Static RAM  
The MCM69F618A is a 1M bit synchronous fast static RAM designed to pro-  
vide a burstable, high performance, secondary cache for the 68K Family, Pow-  
erPC , 486, i960 and Pentium microprocessors. It is organized as 64K  
words of 18 bits each, fabricated with Motorola’s high performance silicon gate  
BiCMOS technology. This device integrates input registers, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in cache data RAM applications. Synchronous design allows precise cycle  
controlwiththeuseofanexternalclock(K). BiCMOScircuitryreducestheoverall  
power consumption of the integrated functions for greater reliability.  
Addresses (SA), data inputs (DQx), and all control signals except output en-  
able (G) and Linear Burst Order (LBO) are clock (K) controlled through positive–  
edge–triggered noninverting registers.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
BurstscanbeinitiatedwitheitherADSPorADSCinputpins. Subsequentburst  
addresses can be generated internally by the MCM69F618A (burst sequence  
operates in linear or interleaved mode dependent upon state of LBO) and con-  
trolled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable SW are provided to allow writes to either individual bytes or to  
both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and  
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are  
asserted with SW. Both bytes are written if either SGW is asserted or if all SBx  
and SW are asserted.  
For read cycles, a flow–through SRAM allows output data to simply flow freely  
from the memory array.  
The MCM69F618A operates from a 3.3 V power supply and all inputs and  
outputs are LVTTL compatible.  
MCM69F618A–8.5 = 8.5 ns access / 12 ns cycle  
MCM69F618A–9 = 9 ns access / 12 ns cycle  
MCM69F618A–10 = 10 ns access / 15 ns cycle  
MCM69F618A–12= 12 ns access / 16.6 ns cycle  
Single 3.3 V + 10%, – 5% Power Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
100 Pin TQFP Package  
BurstRAM is a trademark of Motorola, Inc.  
PowerPC is a trademark of IBM Corp.  
i960 and Pentium are trademarks of Intel Corp.  
REV 1  
4/9/96  
Motorola, Inc. 1996  

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