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MCM69F618CTQ8R PDF预览

MCM69F618CTQ8R

更新时间: 2024-09-19 14:53:15
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理静态存储器内存集成电路
页数 文件大小 规格书
12页 352K
描述
64KX18 CACHE SRAM, 8ns, PQFP100, TQFP-100

MCM69F618CTQ8R 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknown风险等级:5.52
最长访问时间:8 nsJESD-30 代码:R-PQFP-G100
长度:20 mm内存密度:1179648 bit
内存集成电路类型:CACHE SRAM内存宽度:18
功能数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

MCM69F618CTQ8R 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM69F618C/D  
MCM69F618C  
64K x 18 Bit Flow–Through  
BurstRAM Synchronous  
Fast Static RAM  
The MCM69F618C is a 1M–bit synchronous fast static RAM designed to pro-  
vide a burstable, high performance, secondary cache for the 68K Family,  
PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 64K  
words of 18 bits each. This device integrates input registers, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in cache data RAM applications. Synchronous design allows precise cycle  
controlwiththeuseofanexternalclock(K). BiCMOScircuitryreducestheoverall  
power consumption of the integrated functions for greater reliability.  
Addresses (SA), data inputs (DQx), and all control signals except outpu
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through  
positive–edge–triggered noninverting registers.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
BurstscanbeinitiatedwitheitherADSPorADSCinputpins. Subsequentburst  
addresses can be generated internally by the MCM69F618C (burst sequence  
operates in linear or interleaved mode dependent upon the state of LBO) and  
controlled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and initited by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and syn-  
chronous write enable SW are provided to allow writes to either individual bytes  
or to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa  
and SBb controls DQb. Individual bytes are written if the selected byte writes SBx  
are asserted with SW. BothbytesarewrittenifeitherSGW is asserted or if all SBx  
and SW are asserted.  
For read cycles, a flow–through SRAM allows output data to simply flow freely  
from the memory array.  
The MCM69F618C operates from a 3.3 V power supply and all inputs and  
outputs are LVTTL compatible and 5 V tolerant.  
MCM69F618C–7.5 = 7.5 ns Access/12 ns Cycle  
MCM69F618C–8 = 8 ns Access/12 ns Cycle  
MCM69F618C–8.5 = 8.5 ns Access/12 ns Cycle  
MCM69F618C–9 = 9 ns Access/12 ns Cycle  
MCM69F618C–10 = 10 ns Access/15 ns Cycle  
MCM69F618C–12= 12 ns Access/16.6 ns Cycle  
Single 3.3 V + 10%, – 5% Power Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
5 V Tolerant on all Pins (Inputs and I/Os)  
100–Pin TQFP Package  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
i960 and Pentium are trademarks of Intel Corp.  
REV 4  
3/23/98  
Motorola, Inc. 1999  
For More Information On This Product,  
Go to: www.freescale.com  

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