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MCM69F735ZP6.5

更新时间： 2024-11-07 22:06:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
16页 185K
描述
128K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

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MCM69F735ZP6.5 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：BGA,Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
最长访问时间：6.5 nsJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端口数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：2.4 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：MOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

MCM69F735ZP6.5 数据手册

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Order this document  
by MCM69F735/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69F735  
Product Preview  
128K x 36 Bit Flow–Through  
BurstRAM Synchronous  
Fast Static RAM  
The MCM69F735 is a 4M bit synchronous fast static RAM designed to provide  
a burstable, high performance, secondary cache for the PowerPC and other  
high performance microprocessors. It is organized as 128K words of 36 bits  
each. This device integrates input registers, a 2–bit address counter, and high  
speed SRAM onto a single monolithic circuit for reduced parts count in cache  
dataRAMapplications. Synchronousdesignallowsprecisecyclecontrolwiththe  
use of an external clock (K).  
ZP PACKAGE  
PBGA  
CASE 999–01  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable(G) and linear burst order (LBO) are clock (K) controlled through positive–  
edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM69F735 (burst sequence  
operates in linear or interleaved mode dependent upon the state of LBO) and  
controlled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls  
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte  
writes SBx are asserted with SW. All bytes are written if either SGW is asserted  
or if all SBx and SW are asserted.  
For read cycles, a flow–through SRAM allows output data to simply flow freely  
from the memory array.  
The MCM69F735 operates from a 3.3 V core power supply and all outputs  
operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC stan-  
dard JESD8–5 compatible.  
•
MCM69F735 Speed Options  
Flow–Through  
t
Speed  
t
Setup  
0.5 ns  
0.5 ns  
0.5 ns  
Hold  
1 ns  
1 ns  
1 ns  
I
DD  
KHQV  
KHKH  
150 MHz  
133 MHz  
117 MHz  
6.7 ns  
7.5 ns  
8.5 ns  
6 ns  
400 mA  
375 mA  
350 mA  
6.5 ns  
7 ns  
•
3.3 V + 10%, – 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O  
Supply  
•
•
•
•
•
•
•
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
PB1 Version 2.0 Compatible  
JEDEC Standard 119–Pin PBGA Package  
BurstRAM is a trademark of Motorola, Inc.  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
5/23/97  
Motorola, Inc. 1997  
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