Datasheet > MCM69F618C

MCM69F618C

更新时间： 2024-09-18 22:25:55

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
12页	207K
描述
64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

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SEMICONDUCTOR TECHNICAL DATA

MCM69F618C

64K x 18 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F618C is a 1M–bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 64K

words of 18 bits each. This device integrates input registers, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

controlwiththeuseofanexternalclock(K). BiCMOScircuitryreducestheoverall

power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

TQ PACKAGE

TQFP

CASE 983A–01

BurstscanbeinitiatedwitheitherADSPorADSCinputpins. Subsequentburst

addresses can be generated internally by the MCM69F618C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and syn-

chronous write enable SW are provided to allow writes to either individual bytes

or to both bytes. The two bytes are designated as “a” and “b”. SBa controls DQa

and SBb controls DQb. Individual bytes are written if the selected byte writes SBx

are asserted with SW. BothbytesarewrittenifeitherSGW is asserted or if all SBx

and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F618C operates from a 3.3 V power supply and all inputs and

outputs are LVTTL compatible and 5 V tolerant.

•

MCM69F618C–8.5 = 8.5 ns Access / 12 ns Cycle

MCM69F618C–9 = 9 ns Access / 12 ns Cycle

MCM69F618C–10 = 10 ns Access / 15 ns Cycle

MCM69F618C–12= 12 ns Access / 16.6 ns Cycle

Single 3.3 V + 10%, – 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

5 V Tolerant on all Pins (Inputs and I/Os)

100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

REV 2

2/18/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F618C

12 3 4 5 6 7...12

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与MCM69F618C相关器件

型号	品牌	获取价格	描述	数据表
MCM69F618CTQ10	MOTOROLA	获取价格	64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F618CTQ10	NXP	获取价格	64KX18 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F618CTQ10R	NXP	获取价格	64KX18 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F618CTQ10R	MOTOROLA	获取价格	64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F618CTQ12	MOTOROLA	获取价格	64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F618CTQ12	NXP	获取价格	64KX18 CACHE SRAM, 12ns, PQFP100, TQFP-100
MCM69F618CTQ12R	MOTOROLA	获取价格	64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F618CTQ12R	NXP	获取价格	IC,SYNC SRAM,64KX18,BICMOS-TTL,QFP,100PIN,PLASTIC
MCM69F618CTQ7.5	NXP	获取价格	IC,SYNC SRAM,64KX18,BICMOS-TTL,QFP,100PIN,PLASTIC
MCM69F618CTQ8	MOTOROLA	获取价格	64KX18 CACHE SRAM, 8ns, PQFP100, TQFP-100

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