Datasheet > MCM69F536CTQ9R

MCM69F536CTQ9R

更新时间： 2024-11-08 20:25:59

品牌	Logo	应用领域
恩智浦 - NXP		信息通信管理静态存储器内存集成电路
页数	文件大小	规格书
12页	355K
描述
IC,SYNC SRAM,32KX36,BICMOS-TTL,QFP,100PIN,PLASTIC

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MCM69F536CTQ9R 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	compliant
风险等级：	5.52	Is Samacsys：	N
最长访问时间：	9 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	1179648 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.055 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.32 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

MCM69F536CTQ9R 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM69F536C/D

MCM69F536C

32K x 36 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F536C is a 1M–bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 32K

words of 36 bits each. This device integrates input registers, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

controlwiththeuseofanexternalclock(K). BiCMOScircuitryreducestheoverall

power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

TQ PACKAGE

TQFP

CASE 983A–01

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F536C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and

synchronous write enable SW are provided to allow writes to either individual

bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa

controls DQa, SBb controls DQb, and so on. Individual bytes are written if the

selected byte writes SBxare asserted with SW. AllbytesarewrittenifeitherSGW

is asserted or if all SBx and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F536C operates from a 3.3 V power supply and all inputs and

outputs are LVTTL compatible.

•

MCM69F536C–7.5 = 7.5 ns Access/12 ns Cycle

MCM69F536C–8 = 8 ns Access/12 ns Cycle

MCM69F536C–8.5 = 8.5 ns Access/12 ns Cycle

MCM69F536C–9 = 9 ns Access/12 ns Cycle

MCM69F536C–10 = 10 ns Access/15 ns Cycle

MCM69F536C–12 = 12 ns Access/16.6 ns Cycle

Single 3.3 V + 10%, – 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

5 V Tolerant on all Pins (Inputs and I/Os)

100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

REV 5

3/23/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM69F536C

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...12

中文翻译

下载PDF

与MCM69F536CTQ9R相关器件

型号	品牌	获取价格	描述	数据表
MCM69F536TQ10	MOTOROLA	获取价格	Cache SRAM, 32KX36, 10ns, BICMOS, PQFP100, TQFP-100
MCM69F536TQ10R	MOTOROLA	获取价格	32KX36 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F536TQ12	MOTOROLA	获取价格	Cache SRAM, 32KX36, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F536TQ12R	MOTOROLA	获取价格	32KX36 CACHE SRAM, 12ns, PQFP100, TQFP-100
MCM69F536TQ8.5	MOTOROLA	获取价格	32KX36 CACHE SRAM, 8.5ns, PQFP100, TQFP-100
MCM69F536TQ8.5R	MOTOROLA	获取价格	Cache SRAM, 32KX36, 8.5ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ10R	MOTOROLA	获取价格	64KX18 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F618ATQ12	MOTOROLA	获取价格	Cache SRAM, 64KX18, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ12R	MOTOROLA	获取价格	Cache SRAM, 64KX18, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ8.5	MOTOROLA	获取价格	64KX18 CACHE SRAM, 8.5ns, PQFP100, TQFP-100

与MCM69F536CTQ9R相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

17
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69F536CTQ9R

MCM69F536CTQ9R 技术参数

MCM69F536CTQ9R 数据手册

与MCM69F536CTQ9R相关器件

与MCM69F536CTQ9R相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69F536CTQ9R

MCM69F536CTQ9R 技术参数

MCM69F536CTQ9R 数据手册

与MCM69F536CTQ9R相关器件

与MCM69F536CTQ9R相关文章

您还可以找

您在本页遇到什么问题？