Datasheet > MCM69F536TQ10

MCM69F536TQ10

更新时间： 2024-11-08 15:45:35

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		信息通信管理静态存储器
页数	文件大小	规格书
12页	358K
描述
Cache SRAM, 32KX36, 10ns, BICMOS, PQFP100, TQFP-100

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MCM69F536TQ10 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM69F536

Product Preview

32K x 36 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F536 is a 1M bit synchronous fast static RAM designed to provide

a burstable, high performance, secondary cache for the 68K Family, PowerPC ,

486, i960 and Pentium microprocessors. It is organized as 32K words of 36

bits each, fabricated with Motorola’s high performance silicon gate BiCMOS

technology. This device integrates input registers, a 2 bit address counter, and

high speed SRAM onto a single monolithic circuit for reduced parts count in

cache data RAM applications. Synchronous design allows precise cycle control

with the use of an external clock (K). BiCMOS circuitry reduces the overall power

consumption of the integrated functions for greater reliability.

TQ PACKAGE

TQFP

CASE 983A–01

Addresses (SA), data inputs (DQx), and all control signals except output en-

able (G) and Linear Burst Order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F536 (burst sequence op-

eratesinlinearorinterleavedmodedependentuponstateofLBO) and controlled

by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx) and synchronous global write (SGW), and syn-

chronous write enable SW are provided to allow writes to either individual bytes

or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, and so on. Individual bytes are written if the selected

byte writes SBx are asserted with SW. All bytes are written if either SGW is as-

serted or if all SBx and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F536 operates from a 3.3 V power supply and all inputs and

outputs are LVTTL compatible and 5 V tolerant.

•

MCM69F536–8.5 = 8.5 ns access / 12 ns cycle

MCM69F536–10 = 10 ns access / 15 ns cycle

MCM69F536–12 = 12 ns access / 16.6 ns cycle

Single 3.3 V ± 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

5 V Tolerant I/O

100 Pin TQFP Package

•

BurstRAM is a trademark of Motorola, Inc.

PowerPC is a trademark of IBM Corp.

i960 and Pentium are trademarks of Intel Corp.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 2

5/95

Motorola, Inc. 1995

MOTOROLA FAST SRAM

MCM69F536

12 3 4 5 6 7...12

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与MCM69F536TQ10相关器件

型号	品牌	获取价格	描述	数据表
MCM69F536TQ10R	MOTOROLA	获取价格	32KX36 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F536TQ12	MOTOROLA	获取价格	Cache SRAM, 32KX36, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F536TQ12R	MOTOROLA	获取价格	32KX36 CACHE SRAM, 12ns, PQFP100, TQFP-100
MCM69F536TQ8.5	MOTOROLA	获取价格	32KX36 CACHE SRAM, 8.5ns, PQFP100, TQFP-100
MCM69F536TQ8.5R	MOTOROLA	获取价格	Cache SRAM, 32KX36, 8.5ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ10R	MOTOROLA	获取价格	64KX18 CACHE SRAM, 10ns, PQFP100, TQFP-100
MCM69F618ATQ12	MOTOROLA	获取价格	Cache SRAM, 64KX18, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ12R	MOTOROLA	获取价格	Cache SRAM, 64KX18, 12ns, BICMOS, PQFP100, TQFP-100
MCM69F618ATQ8.5	MOTOROLA	获取价格	64KX18 CACHE SRAM, 8.5ns, PQFP100, TQFP-100
MCM69F618ATQ8.5R	MOTOROLA	获取价格	Cache SRAM, 64KX18, 8.5ns, BICMOS, PQFP100, TQFP-100

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