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MCM67H518FN10 PDF预览

MCM67H518FN10

更新时间： 2024-09-17 22:19:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
12页 211K
描述
32K x 18 Bit BurstRAM Synchronous Fast Static RAM

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MCM67H518FN10 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ, LDCC52,.8SQ针数：52
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.82
最长访问时间：10 ns其他特性：SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE
I/O 类型：COMMONJESD-30 代码：S-PQCC-J52
JESD-609代码：e0长度：19.1262 mm
内存密度：589824 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端口数量：1端子数量：52
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
座面最大高度：4.57 mm最大待机电流：0.075 A
最小待机电流：4.75 V子类别：SRAMs
最大压摆率：0.265 mA最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：19.1262 mm
Base Number Matches：1

MCM67H518FN10 数据手册

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Order this document  
by MCM67H518/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67H518  
32K x 18 Bit BurstRAM  
Synchronous Fast Static RAM  
With Burst Counter and Self–Timed Write  
The MCM67H518 is a 589,824 bit synchronous fast static random access  
memory designed to provide a burstable, high–performance, secondary cache  
for the i486 and Pentium microprocessors. It is organized as 32,768 words  
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS  
technology. The device integrates input registers, a 2–bit counter, high speed  
SRAM, and high drive capability outputs onto a single monolithic circuit for re-  
duced parts count implementation of cache data RAM applications. Synchro-  
nous design allows precise cycle control with the use of an external clock (K).  
BiCMOS circuitry reduces the overall power consumption of the integrated func-  
tions for greater reliability.  
FN PACKAGE  
PLASTIC  
CASE 778–02  
PIN ASSIGNMENT  
Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except  
output enable (G) are clock (K) controlled through positive–edge–triggered  
noninverting registers.  
7
6
5
4
3
2
1 52 51 50 49 48 47  
46  
8
9
DQ9  
DQ10  
DQ8  
DQ7  
DQ6  
Bursts canbeinitiatedwitheitheraddressstatusprocessor(ADSP) or address  
status cache controller (ADSC) input pins. Subsequent burst addresses can be  
generated internally by the MCM67H518 (burst sequence imitates that of the  
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.  
The following pages provide more detailed information on burst controls.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased flexibility for incoming signals.  
Dual write enables (LW and UW) are provided to allow individually writeable  
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17  
(the upper bits).  
This device is ideally suited for systems that require wide data bus widths and  
cache memory. See Figure 2 for applications information.  
45  
44  
43  
42  
41  
V
V
10  
CC  
SS  
11  
12  
13  
14  
15  
V
CC  
DQ11  
DQ12  
DQ13  
DQ14  
V
SS  
DQ5  
40 DQ4  
39 DQ3  
38 DQ2  
V
16  
17  
SS  
V
37  
V
V
CC  
SS  
CC  
DQ15  
DQ16  
DQ17  
18  
19  
20  
36  
35 DQ1  
34 DQ0  
21 22 23 24 25 26 27 28 29 30 31 32 33  
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
Fast Access Times: 9/10/12 ns Max  
Byte Writeable via Dual Write Enables  
Internal Input Registers (Address, Data, Control)  
Internally Self–Timed Write Cycle  
ADSP, ADSC, and ADV Burst Control Pins  
Asynchronous Output Enable Controlled Three–State Outputs  
Common Data Inputs and Data Outputs  
3.3 V I/O Compatible  
High Board Density 52–Lead PLCC Package  
ADSP Disabled with Chip Enable (E) – Supports Address Pipelining  
PIN NAMES  
A0 – A14 . . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock  
ADV . . . . . . . . . . . . Burst Address Advance  
LW . . . . . . . . . . . . Lower Byte Write Enable  
UW . . . . . . . . . . . . Upper Byte Write Enable  
ADSC . . . . . . . . . Controller Address Status  
ADSP . . . . . . . . . Processor Address Status  
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ17 . . . . . . . . . . Data Input/Output  
V
V
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
CC  
SS  
NC . . . . . . . . . . . . . . . . . . . . . No Connection  
All power supply and ground pins must be  
connectedforproperoperationofthedevice.  
BurstRAM is a trademark of Motorola, Inc.  
i486 and Pentium are trademarks of Intel Corp.  
REV 3  
5/95  
Motorola, Inc. 1994  
1234567...12

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