MCM67H618BFN9

更新时间： 2024-11-20 22:19:55

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
12页	172K
描述
64K x 18 Bit BurstRAM Synchronous Fast Static RAM

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SEMICONDUCTOR TECHNICAL DATA

MCM67H618B

Advance Information

64K x 18 Bit BurstRAM

Synchronous Fast Static RAM

With Burst Counter and Self–Timed Write

The MCM67H618B is a 1,179,648 bit synchronous fast static random access

memory designed to provide a burstable, high–performance, secondary cache

for the i486 and Pentium microprocessors. It is organized as 65,536 words

of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS

technology. The device integrates input registers, a 2–bit counter, high speed

SRAM, and high drive capability outputs onto a single monolithic circuit for

reduced parts count implementation of cache data RAM applications. Syn-

chronous design allows precise cycle control with the use of an external clock

(K). BiCMOS circuitry reduces the overall power consumption of the integrated

functions for greater reliability.

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENT

1 52 51 50 49 48 47

46 DQ8

Addresses (A0 – A15), data inputs (D0 – D17), and all control signals

except output enable (G) are clock (K) controlled through positive–

edge–triggered noninverting registers.

DQ9

DQ10

45 DQ7

44 DQ6

Bursts can be initiated with either address status processor (ADSP)

or address status cache controller (ADSC) input pins. Subsequent

burst addresses can be generated internally by the MCM67H618B

(burst sequence imitates that of the i486 and Pentium) and controlled

by the burst address advance (ADV) input pin. The following pages pro-

vide more detailed information on burst controls.

DQ11 12

DQ12 13

DQ13 14

DQ14 15

41 DQ5

40 DQ4

39 DQ3

38 DQ2

Write cycles are internally self–timed and are initiated by the rising

edge of the clock (K) input. This feature eliminates complex off–chip

write pulse generation and provides increased flexibility for incoming

signals.

DQ15 18

DQ16 19

DQ17 20

35 DQ1

34 DQ0

21 22 23 24 25 26 27 28 29 30 31 32 33

Dual write enables (LW and UW) are provided to allow individually

writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW

controls DQ9 – DQ17 (the upper bits).

This device is ideally suited for systems that require wide data bus

widths and cache memory. See Figure 2 for applications information.

PIN NAMES

A0 – A15 . . . . . . . . . . . . . . . . Address Inputs

K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock

ADV . . . . . . . . . . . . Burst Address Advance

LW . . . . . . . . . . . . Lower Byte Write Enable

UW . . . . . . . . . . . . Upper Byte Write Enable

ADSC . . . . . . . . . Controller Address Status

ADSP . . . . . . . . . Processor Address Status

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 – DQ17 . . . . . . . . . . Data Input/Output

•

Single 5 V ± 5% Power Supply

Fast Access Times: 9/10/12 ns Max

Byte Writeable via Dual Write Enables

Internal Input Registers (Address, Data, Control)

Internally Self–Timed Write Cycle

ADSP, ADSC, and ADV Burst Control Pins

Asynchronous Output Enable Controlled Three–State Outputs

Common Data Inputs and Data Outputs

3.3 V I/O Compatible

High Board Density 52–Lead PLCC Package

ADSP Disabled with Chip Enable (E) — Supports Address Pipelining

. . . . . . . . . . . . . . . . + 5 V Power Supply

. . . . . . . . . . . . . . . . . . . . . . . . . . Ground

All power supply and ground pins must be con-

nected for proper operation of the device.

i486 and Pentium are trademarks of Intel Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

7/15/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM67H618B

12 3 4 5 6 7...12

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与MCM67H618BFN9相关器件

型号	品牌	获取价格	描述	数据表
MCM67H618BFN9R	MOTOROLA	获取价格	64KX18 CACHE SRAM, 9ns, PQCC52, PLASTIC, LCC-52
MCM67H618FN12	MOTOROLA	获取价格	64KX18 CACHE SRAM, PQCC52, PLASTIC, LCC-52
MCM67H618FN18	MOTOROLA	获取价格	Cache SRAM, 64KX18, 18ns, BICMOS, PQCC52, PLASTIC, LCC-52
MCM67H618FN9	MOTOROLA	获取价格	64KX18 CACHE SRAM, 9ns, PQCC52, PLASTIC, LCC-52
MCM67J518	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RA
MCM67J518AFN5	MOTOROLA	获取价格	32KX18 CACHE SRAM, 5ns, PQCC52, PLASTIC, LCC-52
MCM67J518AFN7	MOTOROLA	获取价格	暂无描述
MCM67J518FN6	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RA
MCM67J518FN7	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RA
MCM67J518FN9	MOTOROLA	获取价格	32K x 18 Bit BurstRAM Synchronous Fast Static RA

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