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SEMICONDUCTOR TECHNICAL DATA
MCM67J518
32K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
The MCM67J518 is a 589,824 bit synchronous static random access memory
designed to provide a burstable, high–performance, secondary cache for the
i486 and Pentium microprocessors. It is organized as 32,768 words of 18
bits, fabricated withMotorola’s high–performance silicon–gate BiCMOS technol-
ogy. The device integrates input registers, a 2–bit counter, high speed SRAM,
and high drive registered output drivers onto a single monolithic circuit for re-
duced parts count implementation of cache data RAM applications. Synchro-
nous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered
noninverting registers.
7
6
5
4
3
2
1 52 51 50 49 48 47
46
This device contains output registers for pipeline operations. At the rising edge
of K, the RAM provides the output data from the previous cycle.
Output enable (G) is asynchronous for maximum system design flexibility.
Burst can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM67J518 (burst sequence imitates that of the
i486) and controlled by the burst address advance (ADV) input pin. The following
pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
8
9
DQ9
DQ10
DQ8
DQ7
DQ6
45
44
43
42
41
40
39
V
V
10
CC
SS
11
12
13
14
15
V
CC
DQ11
DQ12
DQ13
DQ14
V
SS
DQ5
DQ4
DQ3
V
16
17
38
37
DQ2
SS
V
V
CC
SS
DQ15
DQ16
DQ17
18
19
20
36
35
34
V
CC
DQ1
DQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
•
•
Single 5 V ± 5% Power Supply
Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz,
9 ns/66 MHz
PIN NAMES
A0 – A14 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
•
•
•
•
•
•
•
•
•
•
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Output Registers for Pipelined Applications
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
V
CC
V
SS
. . . . . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
High Board Density 52–Lead PLCC Package
ADSP Disabled with Chip Enable (E) – Supports Address Pipelining
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
REV 3
5/95
Motorola, Inc. 1994
MOTOROLA FAST SRAM
MCM67J518
1
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