MC74VHC125
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
http://onsemi.com
The MC74VHC125 requires the 3−state control input (OE) to be set
High to place the output into the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
14−LEAD SOIC
14−LEAD TSSOP
DT SUFFIX
D SUFFIX
CASE 751A
CASE 948G
• High Speed: t = 3.8ns (Typ) at V = 5 V
PD
CC
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
14−LEAD SOIC EIAJ
M SUFFIX
CASE 965
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
OLP
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
OE1
A1
1
2
14
13 OE4
12
V
CC
Machine Model; > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
Y1
3
4
A4
OE2
11 Y4
A2
Y2
5
6
7
10 OE3
9
8
A3
Y3
GND
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC125DG
SOIC
55 Units/Rail
2500 Units/Reel
50 Units/Rail
MC74VHC125DTR2G TSSOP
MC74VHC125MG
SOIC EIAJ
SOIC
MC74VHC125DR2G
2500 Units/Reel
2000 Units/Reel
MC74VHC125MELG SOEIAJ
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 6
MC74VHC125/D