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MC74VHC125DTR2 PDF预览

MC74VHC125DTR2

更新时间: 2024-02-07 08:49:14
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 96K
描述
AHC/VHC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, TSSOP-14

MC74VHC125DTR2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.41
控制类型:ENABLE LOW系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):16 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MC74VHC125DTR2 数据手册

 浏览型号MC74VHC125DTR2的Datasheet PDF文件第2页浏览型号MC74VHC125DTR2的Datasheet PDF文件第3页浏览型号MC74VHC125DTR2的Datasheet PDF文件第4页浏览型号MC74VHC125DTR2的Datasheet PDF文件第5页浏览型号MC74VHC125DTR2的Datasheet PDF文件第6页浏览型号MC74VHC125DTR2的Datasheet PDF文件第7页 
MC74VHC125  
Quad Bus Buffer  
with 3−State Control Inputs  
The MC74VHC125 is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
www.onsemi.com  
The MC74VHC125 requires the 3−state control input (OE) to be set  
High to place the output into the high impedance state.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7 V, allowing the interface of 5 V  
systems to 3 V systems.  
14−LEAD SOIC  
14−LEAD TSSOP  
DT SUFFIX  
D SUFFIX  
CASE 751A  
CASE 948G  
Features  
High Speed: t = 3.8ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
PIN CONNECTION AND  
MARKING DIAGRAM  
High Noise Immunity: V  
= V  
= 28% V  
NIH  
NIL CC  
(Top View)  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
Designed for 2 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
Y1  
3
4
A4  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
OE2  
11 Y4  
A2  
Y2  
5
6
7
10 OE3  
ESD Performance: Human Body Model; > 2000 V,  
Machine Model; > 200 V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
9
8
A3  
Y3  
GND  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 6 of this data sheet.  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
LOGIC DIAGRAM  
FUNCTION TABLE  
Active−Low Output Enables  
dimensions section on page 2 of this data sheet.  
VHC125  
Inputs Output  
2
3
A1  
Y1  
A
OE  
Y
1
OE1  
H
L
L
L
H
L
5
4
6
X
H
Z
A2  
Y2  
Y3  
OE2  
9
8
A3  
10  
OE3  
12  
13  
11  
A4  
Y4  
OE4  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
October, 2017 − Rev. 8  
MC74VHC125/D  

MC74VHC125DTR2 替代型号

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74VHC125MTCX ONSEMI

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