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MC74VHC126ML2 PDF预览

MC74VHC126ML2

更新时间: 2024-11-04 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 163K
描述
IC,BUFFER/DRIVER,SINGLE,4-BIT,AHC/VHC-CMOS,SOP,14PIN,PLASTIC

MC74VHC126ML2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP14,.3Reach Compliance Code:not_compliant
风险等级:5.92控制类型:ENABLE HIGH
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:4功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:2/5.5 V
Prop。Delay @ Nom-Sup:8.5 ns认证状态:Not Qualified
子类别:Bus Driver/Transceivers表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MC74VHC126ML2 数据手册

 浏览型号MC74VHC126ML2的Datasheet PDF文件第2页浏览型号MC74VHC126ML2的Datasheet PDF文件第3页浏览型号MC74VHC126ML2的Datasheet PDF文件第4页浏览型号MC74VHC126ML2的Datasheet PDF文件第5页浏览型号MC74VHC126ML2的Datasheet PDF文件第6页浏览型号MC74VHC126ML2的Datasheet PDF文件第7页 
with 3–State Control Inputs  
The MC74VHC126 is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves  
noninverting high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining CMOS low power dissipation.  
The MC74VHC126 requires the 3–state control input (OE) to be set  
Low to place the output into high impedance.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
14–LEAD SOIC  
14–LEAD TSSOP  
DT SUFFIX  
D SUFFIX  
CASE 751A  
CASE 948G  
High Speed: t  
= 3.8ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
= V  
= 28% V  
NIL CC  
NIH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2V to 5.5V Operating Range  
14–LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
Low Noise: V  
= 0.8V (Max)  
OLP  
PIN CONNECTION AND  
MARKING DIAGRAM (Top View)  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
Y1  
3
4
A4  
LOGIC DIAGRAM  
OE2  
11 Y4  
Active–High Output Enables  
A2  
Y2  
5
6
7
10 OE3  
2
1
3
6
A1  
9
8
A3  
Y3  
Y1  
GND  
OE1  
5
4
For detailed package marking information, see the Marking  
Diagram section on page 5 of this data sheet.  
A2  
Y2  
Y3  
OE2  
9
8
A3  
ORDERING INFORMATION  
10  
OE3  
Device  
Package  
SOIC  
Shipping  
12  
13  
11  
A4  
Y4  
MC74VHC126D  
MC74VHC126DT  
MC74VHC126M  
55 Units/Rail  
96 Units/Rail  
50 Units/Rail  
OE4  
TSSOP  
FUNCTION TABLE  
SOIC EIAJ  
VHC126  
Inputs Output  
A
OE  
Y
H
L
X
H
H
L
H
L
Z
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 1  
MC74VHC126/D  

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