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MC74VHC138D

更新时间： 2024-11-23 22:58:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
7页 168K
描述
3-to-8 Line Decoder

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中文翻译

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MC74VHC138D 数据手册

 浏览型号MC74VHC138D的Datasheet PDF文件第2页浏览型号MC74VHC138D的Datasheet PDF文件第3页浏览型号MC74VHC138D的Datasheet PDF文件第4页浏览型号MC74VHC138D的Datasheet PDF文件第5页浏览型号MC74VHC138D的Datasheet PDF文件第6页浏览型号MC74VHC138D的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC138 is an advanced high speed CMOS 3–to–8 decoder  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
When the device is enabled, three Binary Select inputs (A0 – A2)  
determine which one of the outputs (Y0 – Y7) will go Low. When enable input  
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited  
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade  
connection and for use as an address decoder for memory systems.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
D SUFFIX  
16–LEAD SOIC PACKAGE  
CASE 751B–05  
DT SUFFIX  
16–LEAD TSSOP PACKAGE  
CASE 948F–01  
•
•
•
•
•
•
•
•
•
•
•
High Speed: t  
= 5.7ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2V to 5.5V Operating Range  
= V  
= 28% V  
NIH  
NIL CC  
Low Noise: V  
= 0.8 V (Max)  
M SUFFIX  
16–LEAD SOIC EIAJ PACKAGE  
CASE 966–01  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 122 FETs or 30.5 Equivalent Gates  
ORDERING INFORMATION  
MC74VHCXXXD  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
FUNCTION TABLE  
Inputs  
Outputs  
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PIN ASSIGNMENT  
A0  
A1  
1
2
16  
15  
14  
13  
V
CC  
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Y0  
Y1  
Y2  
Y3  
Y4  
3
4
5
6
A2  
E1  
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
E2  
E3  
12  
11  
H
H
7
8
10  
9
Y7  
Y5  
Y6  
H = high level (steady state); L = low level (steady state);  
X = don’t care  
GND  
15  
Y0  
1
14  
13  
12  
A0  
A1  
A2  
Y1  
Y2  
Y3  
SELECT  
INPUTS  
2
3
ACTIVE–LOW  
OUTPUTS  
11  
10  
Y4  
Y5  
Y6  
Y7  
9
7
6
5
E3  
E2  
E1  
ENABLE  
INPUTS  
LOGIC DIAGRAM  
4
6/97  
REV 1  
Motorola, Inc. 1997  
1234567

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